- 您现在的位置：买卖IC网 > PDF目录69322 > RK80546KG0802MM (INTEL CORP) 64-BIT, 3000 MHz, MICROPROCESSOR, CPGA604 PDF资料下载
参数资料
| 型号： | RK80546KG0802MM |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 3000 MHz, MICROPROCESSOR, CPGA604 |
| 封装： | FLIP CHIP, MICRO PGA-604 |
| 文件页数： | 53/106页 |
| 文件大小： | 4724K |
| 代理商： | RK80546KG0802MM |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页当前第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
50
Datasheet
Signal Definitions
IERR#
O
IERR# (Internal Error) is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor front side bus. This transaction
may optionally be converted to an external error signal (e.g., NMI) by
system core logic. The processor will keep IERR# asserted until the
assertion of RESET#.
This signal does not have on-die termination and must be terminated
at the end agent.
3
IGNNE#
I
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore
a numeric error and continue to execute noncontrol floating-point
instructions. If IGNNE# is deasserted, the processor generates an
exception on a noncontrol floating-point instruction if a previous floating-
point instruction caused an error. IGNNE# has no effect when the NE bit in
control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this
signal following an I/O write instruction, it must be valid along with the
TRDY# assertion of the corresponding I/O write bus transaction.
3
INIT#
I
INIT# (Initialization), when asserted, resets integer registers inside all
processors without affecting their internal caches or floating-point registers.
Each processor then begins execution at the power-on Reset vector
configured during power-on configuration. The processor continues to
handle snoop requests during INIT# assertion. INIT# is an asynchronous
signal and must connect the appropriate pins of all processor front side bus
agents.
If INIT# is sampled active on the active to inactive transition of RESET#,
then the processor executes its Built-in Self-Test (BIST).
3
LINT[1:0]
I
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all
front side bus agents. When the APIC functionality is disabled, the LINT0/
INTR signal becomes INTR, a maskable interrupt request signal, and
LINT1/NMI becomes NMI, a nonmaskable interrupt. INTR and NMI are
backward compatible with the signals of those names on the Pentium
processor. Both signals are asynchronous.
These signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because
the APIC is enabled by default after Reset, operation of these pins as
LINT[1:0] is the default configuration.
3
LOCK#
I/O
LOCK# indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of all processor front side
bus agents. For a locked sequence of transactions, LOCK# is asserted
from the beginning of the first transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the
processor front side bus, it will wait until it observes LOCK# deasserted.
This enables symmetric agents to retain ownership of the processor front
side bus throughout the bus locked operation and ensure the atomicity of
lock.
4
Table 4-1. Signal Definitions (Sheet 6 of 10)
Name
Type
Description
Notes
相关PDF资料 |
PDF描述 |
|---|---|
| RK80546PG0801M | 32-BIT, 3000 MHz, MICROPROCESSOR, CPGA478 |
| RK80546PE0721M | 32-BIT, 2800 MHz, MICROPROCESSOR, CPGA478 |
| RL5C478A | PCI BUS CONTROLLER, PQFP256 |
| RM100355WFQMLV | 100K SERIES, LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CQFP24 |
| RM48L950PGET | 32-BIT, FLASH, 200 MHz, RISC MICROCONTROLLER, PQFP144 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| RK80546KG0802MMS L7ZF | 制造商:Intel 功能描述:MPU Xeon NetBurst 64-Bit 90nm 3GHz 604-Pin FCmPGA4 制造商:Intel 功能描述:XEON 3E GHZ,2M,800MHZ,FC MPGA4 - Trays |
| RK80546KG0881M S L7PF | 制造商:Intel 功能描述:INTEL XEON, 3.2DGHZ,1M,800MHZ,FC-MPGA4 - Trays |
| RK80546KG0882MMS L7ZE | 制造商:Intel 功能描述:XEON 3.2,2M,800MHZ,FC-MPGA4 - Trays |
| RK80546KG1041M | 制造商:Rochester Electronics LLC 功能描述:XEON 3.6GHZ,1M,800MHZ,FC MPGA4 - Bulk |
| RK80546KG1041M S L7PH | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU XEON 90NM 3.6GHZ 604PIN PGA - Trays |
发布紧急采购，3分钟左右您将得到回复。