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参数资料
| 型号： | RK80546KG0802MM |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 3000 MHz, MICROPROCESSOR, CPGA604 |
| 封装： | FLIP CHIP, MICRO PGA-604 |
| 文件页数： | 91/106页 |
| 文件大小： | 4724K |
| 代理商： | RK80546KG0802MM |
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Datasheet
85
7
Features
7.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples its hardware
configuration at reset, on the active-to-inactive transition of RESET#. For specifics on these
options, please refer to Table 7-1.
The sampled information configures the processor for subsequent operation. These configuration
options cannot be changed except by another reset. All resets reconfigure the processor, for reset
purposes, the processor does not distinguish between a “warm” reset and a “power-on” reset.
NOTES:
1. Asserting this signal during RESET# will select the corresponding option.
2. Address pins not identified in this table as configuration options should not be asserted during RESET#.
3. The 64-bit Intel Xeon processor with 2 MB L2 cache only uses the BR0# and BR1# signals. Platforms
must not utilize BR2# and BR3# signals.
7.2
Clock Control and Low Power States
The processor allows the use of HALT, Stop Grant and Sleep states to reduce power consumption
by stopping the clock to internal sections of the processor, depending on each particular state. See
Figure 7-1 for a visual representation of the processor low power states.
The 64-bit Intel Xeon processor with 2 MB L2 cache supports the Enhanced HALT Power Down
state. Refer to Figure 7-1 and the following sections. Note: Not all Intel Xeon processors are
capable of supporting the Enhanced HALT state. More details on which processor frequencies
support the Enhanced HALT state are provided in the 64-bit Intel Xeon Processor with 800
MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update.
The Stop Grant state requires chipset and BIOS support on multiprocessor systems. In a
multiprocessor system, all the STPCLK# signals are bussed together, thus all processors are
affected in unison. The Hyper-Threading Technology feature adds the conditions that all logical
processors share the same STPCLK# signal internally. When the STPCLK# signal is asserted, the
processor enters the Stop Grant state, issuing a Stop Grant Special Bus Cycle (SBC) for each
processor or logical processor. The chipset needs to account for a variable number of processors
Table 7-1. Power-On Configuration Option Pins
Configuration Option
Pin
Notes
Output tri state
SMI#
1,2
Execute BIST (Built-In Self Test)
INIT#
1,2
In Order Queue de-pipelining (set IOQ depth to 1)
A7#
1,2
Disable MCERR# observation
A9#
1,2
Disable BINIT# observation
A10#
1,2
Disable bus parking
A15#
1,2
Symmetric agent arbitration ID
BR[3:0]#
1,2,3
Disable Hyper-Threading Technology
A31#
1,2
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RK80546KG0802MMS L7ZF | 制造商:Intel 功能描述:MPU Xeon NetBurst 64-Bit 90nm 3GHz 604-Pin FCmPGA4 制造商:Intel 功能描述:XEON 3E GHZ,2M,800MHZ,FC MPGA4 - Trays |
| RK80546KG0881M S L7PF | 制造商:Intel 功能描述:INTEL XEON, 3.2DGHZ,1M,800MHZ,FC-MPGA4 - Trays |
| RK80546KG0882MMS L7ZE | 制造商:Intel 功能描述:XEON 3.2,2M,800MHZ,FC-MPGA4 - Trays |
| RK80546KG1041M | 制造商:Rochester Electronics LLC 功能描述:XEON 3.6GHZ,1M,800MHZ,FC MPGA4 - Bulk |
| RK80546KG1041M S L7PH | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU XEON 90NM 3.6GHZ 604PIN PGA - Trays |
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