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参数资料
| 型号： | RK80546KG0802MM |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 3000 MHz, MICROPROCESSOR, CPGA604 |
| 封装： | FLIP CHIP, MICRO PGA-604 |
| 文件页数： | 48/106页 |
| 文件大小： | 4724K |
| 代理商： | RK80546KG0802MM |
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46
Datasheet
Signal Definitions
BCLK[1:0]
I
The differential bus clock pair BCLK[1:0] determines the front side bus
frequency. All processor front side bus agents must receive these signals
to drive their outputs and latch their inputs.
All external timing parameters are specified with respect to the rising edge
of BCLK0 crossing VCROSS.
4
BINIT#
I/O
BINIT# (Bus Initialization) may be observed and driven by all processor
front side bus agents and if used, must connect the appropriate pins of all
such agents. If the BINIT# driver is enabled during power on configuration,
BINIT# is asserted to signal any bus condition that prevents reliable future
information.
If BINIT# observation is enabled during power-on configuration (see
Figure 7.1) and BINIT# is sampled asserted, symmetric agents reset their
bus LOCK# activity and bus request arbitration state machines. The bus
agents do not reset their I/O Queue (IOQ) and transaction tracking state
machines upon observation of BINIT# assertion. Once the BINIT#
assertion has been observed, the bus agents will re-arbitrate for the front
side bus and attempt completion of their bus queue and IOQ entries.
If BINIT# observation is disabled during power-on configuration, a central
agent may handle an assertion of BINIT# as appropriate to the error
handling architecture of the system.
Since multiple agents may drive this signal at the same time, BINIT# is a
wired-OR signal which must connect the appropriate pins of all processor
front side bus agents. In order to avoid wired-OR glitches associated with
simultaneous edge transitions driven by multiple drivers, BINIT# is
activated on specific clock edges and sampled on specific clock edges
4
BNR#
I/O
BNR# (Block Next Request) is used to assert a bus stall by any bus agent
who is unable to accept new bus transactions. During a bus stall, the
current bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time,
BNR# is a wired-OR signal which must connect the appropriate pins of all
processor front side bus agents. In order to avoid wired-OR glitches
associated with simultaneous edge transitions driven by multiple drivers,
BNR# is activated on specific clock edges and sampled on specific clock
edges.
4
BOOT_
SELECT
I
The BOOT_SELECT input informs the processor whether the platform
supports the 64-bit Intel Xeon processor with 2 MB L2 cache. The
processor will not operate if this signal is low. This input has a weak pull-up
to VTT.
BPM[5:0]#
I/O
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor
signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance. BPM[5:0]# should connect the appropriate pins of all front
side bus agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port.
PRDY# is a processor output used by debug tools to determine processor
debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP port.
PREQ# is used by debug tools to request debug operation of the
processors.
BPM[5:4]# must be bussed to all bus agents. Please refer to the
appropriate platform design guidelines for more detailed information.
These signals do not have on-die termination and must be terminated
at the end agent.
3
Table 4-1. Signal Definitions (Sheet 2 of 10)
Name
Type
Description
Notes
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RK80546KG0802MMS L7ZF | 制造商:Intel 功能描述:MPU Xeon NetBurst 64-Bit 90nm 3GHz 604-Pin FCmPGA4 制造商:Intel 功能描述:XEON 3E GHZ,2M,800MHZ,FC MPGA4 - Trays |
| RK80546KG0881M S L7PF | 制造商:Intel 功能描述:INTEL XEON, 3.2DGHZ,1M,800MHZ,FC-MPGA4 - Trays |
| RK80546KG0882MMS L7ZE | 制造商:Intel 功能描述:XEON 3.2,2M,800MHZ,FC-MPGA4 - Trays |
| RK80546KG1041M | 制造商:Rochester Electronics LLC 功能描述:XEON 3.6GHZ,1M,800MHZ,FC MPGA4 - Bulk |
| RK80546KG1041M S L7PH | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU XEON 90NM 3.6GHZ 604PIN PGA - Trays |
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