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参数资料
| 型号： | RK80546KG0802MM |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 3000 MHz, MICROPROCESSOR, CPGA604 |
| 封装： | FLIP CHIP, MICRO PGA-604 |
| 文件页数： | 55/106页 |
| 文件大小： | 4724K |
| 代理商： | RK80546KG0802MM |
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52
Datasheet
Signal Definitions
RESET#
I
Asserting the RESET# signal resets all processors to known states and
invalidates their internal caches without writing back any of their contents.
For a power-on Reset, RESET# must stay active for at least 1 ms after VCC
and BCLK have reached their proper specifications. On observing active
RESET#, all front side bus agents will deassert their outputs within two
clocks. RESET# must not be kept asserted for more than 10 ms while
PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive transition of
RESET# for power-on configuration. These configuration options are
described in the Section 7.1.
This signal does not have on-die termination and must be terminated
at the end agent.
4
RS[2:0]#
I
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect
the appropriate pins of all processor front side bus agents.
4
RSP#
I
RSP# (Response Parity) is driven by the response agent (the agent
responsible for completion of the current transaction) during assertion of
RS[2:0]#, the signals for which RSP# provides parity protection. It must
connect to the appropriate pins of all processor front side bus agents.
A correct parity signal is high if an even number of covered signals are low
and low if an odd number of covered signals are low. While RS[2:0]# = 000,
RSP# is also high, since this indicates it is not being driven by any agent
guaranteeing correct parity.
4
SKTOCC#
O
SKTOCC# (Socket occupied) will be pulled to ground by the processor to
indicate that the processor is present. There is no connection to the
processor silicon for this signal.
SLEW_CTRL
I
The front side bus slew rate control input, SLEW_CTRL, is used to
establish distinct edge rates for middle and end agents.
SLP#
I
SLP# (Sleep), when asserted in Stop-Grant state, causes processors to
enter the Sleep state. During Sleep state, the processor stops providing
internal clock signals to all units, leaving only the Phase-Lock Loop (PLL)
still operating. Processors in this state will not recognize snoops or
interrupts. The processor will only recognize the assertion of the RESET#
signal, deassertion of SLP#, and removal of the BCLK input while in Sleep
state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and
processor core units.
3
SMB_PRT
O
The SMBus present (SMB_PRT) pin is defined to inform the platform if the
installed processor includes SMBus components such as the integrated
thermal sensor and the processor information ROM (PIROM). This pin is
tied to VSS by the processor if these features are not present. Platforms
utilizing this pin should use a pull up resistor to the appropriate voltage
level for the logic tied to this pin. Because this pin does not connect to the
processor silicon, any platform voltage and termination value is acceptable.
SMI#
I
SMI# (System Management Interrupt) is asserted asynchronously by
system logic. On accepting a System Management Interrupt, processors
save the current state and enter System Management Mode (SMM). An
SMI Acknowledge transaction is issued, and the processor begins program
execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will tri-
state its outputs.
3
Table 4-1. Signal Definitions (Sheet 8 of 10)
Name
Type
Description
Notes
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RK80546KG0802MMS L7ZF | 制造商:Intel 功能描述:MPU Xeon NetBurst 64-Bit 90nm 3GHz 604-Pin FCmPGA4 制造商:Intel 功能描述:XEON 3E GHZ,2M,800MHZ,FC MPGA4 - Trays |
| RK80546KG0881M S L7PF | 制造商:Intel 功能描述:INTEL XEON, 3.2DGHZ,1M,800MHZ,FC-MPGA4 - Trays |
| RK80546KG0882MMS L7ZE | 制造商:Intel 功能描述:XEON 3.2,2M,800MHZ,FC-MPGA4 - Trays |
| RK80546KG1041M | 制造商:Rochester Electronics LLC 功能描述:XEON 3.6GHZ,1M,800MHZ,FC MPGA4 - Bulk |
| RK80546KG1041M S L7PH | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU XEON 90NM 3.6GHZ 604PIN PGA - Trays |
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