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参数资料
型号： RK80546KG0802MM
厂商： INTEL CORP
元件分类： 微控制器/微处理器
英文描述： 64-BIT, 3000 MHz, MICROPROCESSOR, CPGA604
封装： FLIP CHIP, MICRO PGA-604
文件页数： 57/106页
文件大小： 4724K
代理商： RK80546KG0802MM
54
Datasheet
Signal Definitions
NOTES:
1. The 64-bit Intel Xeon processor with 2 MB L2 cache only supports BR0# and BR1#. However, platforms
must terminate BR2# and BR3# to VTT.
2. For this pin on the 64-bit Intel Xeon processor with 2 MB L2 cache, the maximum number of symmetric
agents is one. Maximum number of central agents is zero.
3. For this pin on the 64-bit Intel Xeon processor with 2 MB L2 cache, the maximum number of symmetric
agents is two. Maximum number of central agents is zero.
4. For this pin on the 64-bit Intel Xeon processor with 2 MB L2 cache, the maximum number of symmetric
agents is two. Maximum number of central agents is one.
VCCIOPLL
I
VCCIOPLL provides isolated power for digital portion of the internal
processor core PLL’s. Refer to the appropriate platform design guidelines
for complete implementation details.
VCCPLL
I
The on-die PLL filter solution will not be implemented on this
platform. The VCCPLL input should be left unconnected.
VCCSENSE
VSSSENSE
O
VCCSENSE and VSSSENSE provide an isolated, low impedance
connection to the processor core power and ground. They can be
used to sense or measure power near the silicon with little noise.
VID[5:0]
O
VID[5:0] (Voltage ID) pins are used to support automatic selection of power
supply voltages (VCC). These are open drain signals that are driven by the
processor and must be pulled up through a resistor. Conversely, the VR
output must be disabled prior to the voltage supply for these pins becomes
invalid. The VID pins are needed to support processor voltage specification
variations. See Table 2-3 for definitions of these pins. The VR must supply
the voltage that is requested by these pins, or disable itself.
VIDPWRGD
I
The processor requires this input to determine that the supply voltage for
BSEL[1:0] and VID[5:0] is stable and within specification.
VSSA
I
VSSA provides an isolated, internal ground for internal PLL’s. Do not
connect directly to ground. This pin is to be connected to VCCA and
VCCIOPLL through a discrete filter circuit.
VTT
P
The front side bus termination voltage input pins. Refer to Table 2-8 for
further details.
VTTEN
O
The VTTEN can be used as an output enable for the VTT regulator in the
event an incompatible processor is inserted into the platform. There is no
connection to the processor silicon for this signal and it must be pulled up
through a resistor. Refer to the appropriate platform design guidelines for
implementation details.
Table 4-1. Signal Definitions (Sheet 10 of 10)
Name
Type
Description
Notes
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RK80546KG0802MMS L7ZF 制造商:Intel 功能描述:MPU Xeon NetBurst 64-Bit 90nm 3GHz 604-Pin FCmPGA4 制造商:Intel 功能描述:XEON 3E GHZ,2M,800MHZ,FC MPGA4 - Trays
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RK80546KG1041M S L7PH 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU XEON 90NM 3.6GHZ 604PIN PGA - Trays
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