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| 型号： | RK80546KG0802MM |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 3000 MHz, MICROPROCESSOR, CPGA604 |
| 封装： | FLIP CHIP, MICRO PGA-604 |
| 文件页数： | 23/106页 |
| 文件大小： | 4724K |
| 代理商： | RK80546KG0802MM |
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Datasheet
23
Electrical Specifications
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals whose timings are specified with respect to
rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source
synchronous signals which are relative to their respective strobe lines (data and address) as well as
rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can
become active at any time during the clock cycle. Table 2-4 identifies which signals are common
clock, source synchronous and asynchronous.
NOTES:
1. Refer to Section 4 for signal descriptions.
2. The 64-bit Intel Xeon processor with 2 MB L2 cache only uses BR0# and BR1#. BR2# and BR3# must be
terminated to VTT. For additional details regarding the BR[3:0]# signals, see Section 4 and Section 7.1.
3. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration
options. See Section 7.1 for details.
4. These signals may be driven simultaneously by multiple agents (wired-OR).
Table 2-4. Front Side Bus Signal Groups
Signal Group
Type
Signals1
AGTL+ Common Clock Input
Synchronous to BCLK[1:0]
BPRI#, BR[3:1]#2,3, DEFER#, RESET#,
RS[2:0]#, RSP#, TRDY#
AGTL+ Common Clock I/O
Synchronous to BCLK[1:0]
ADS#, AP[1:0]#, BINIT#4, BNR#4, BPM[5:0]#,
BR0#2,3, DBSY#, DP[3:0]#, DRDY#, HIT#4,
HITM#4, LOCK#, MCERR#4
AGTL+ Source Synchronous I/O
Synchronous to assoc.
strobe
AGTL+ Strobe I/O
Synchronous to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
AGTL Asynchronous Output
Asynchronous
FERR#/PBE#, IERR#, PROCHOT#
GTL+ Asynchronous Input
Asynchronous
A20M#, FORCEPR#, IGNNE#, INIT#3, LINT0/
INTR, LINT1/NMI, SMI#3, SLP#, STPCLK#
GTL+ Asynchronous Output
Asynchronous
THERMTRIP#
Front Side Bus Clock
Clock
BCLK1, BCLK0
TAP Input
Synchronous to TCK
tck, tdi, tms, trst#
TAP Output
Synchronous to TCK
TDO
Power/Other
BOOT_SELECT, BSEL[1:0], COMP[1:0],
GTLREF[3:0], ODTEN, OPTIMIZED/
COMPAT#, PWRGOOD, Reserved,
SKTOCC#, SLEW_CTRL, SMB_PRT,
TEST_BUS, TESTHI[6:0], THERMDA,
THERMDC, VCC, VCCA, VCCIOPLL, VCCPLL,
VCCSENSE, VID[5:0], VSS, VSSA,
VSSSENSE, VTT, VIDPWRGD, VTTEN
Signals
Associated Strobe
REQ[4:0]#,A[16:3]#3
ADSTB0#
A[35:17]#3
ADSTB1#
D[15:0]#, DBI0#
DSTBP0#, DSTBN0#
D[31:16]#, DBI1#
DSTBP1#, DSTBN1#
D[47:32]#, DBI2#
DSTBP2#, DSTBN2#
D[63:48]#, DBI3#
DSTBP3#, DSTBN3#
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