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参数资料
| 型号： | RK80546KG0802MM |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 3000 MHz, MICROPROCESSOR, CPGA604 |
| 封装： | FLIP CHIP, MICRO PGA-604 |
| 文件页数： | 47/106页 |
| 文件大小： | 4724K |
| 代理商： | RK80546KG0802MM |
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Datasheet
45
4
Signal Definitions
4.1
Signal Definitions
Table 4-1. Signal Definitions (Sheet 1 of 10)
Name
Type
Description
Notes
A[35:3]#
I/O
A[35:3]# (Address) define a 236-byte physical memory address space. In
sub-phase 1 of the address phase, these pins transmit the address of a
transaction. In sub-phase 2, these pins transmit transaction type
information. These signals must connect the appropriate pins of all agents
on the front side bus. A[35:3]# are protected by parity signals AP[1:0]#.
A[35:3]# are source synchronous signals and are latched into the receiving
buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processors sample a
subset of the A[35:3]# pins to determine their power-on configuration. See
4
A20M#
I
If A20M# (Address-20 Mask) is asserted, the processor masks physical
address bit 20 (A20#) before looking up a line in any internal cache and
before driving a read/write transaction on the bus. Asserting A20M#
emulates the 8086 processor's address wrap-around at the 1 MB
boundary. Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this
signal following an I/O write instruction, it must be valid along with the
TRDY# assertion of the corresponding I/O write bus transaction.
3
ADS#
I/O
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[35:3]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode,
internal snoop, or deferred reply ID match operations associated with the
new transaction. This signal must connect the appropriate pins on all (800
MHz) front side bus agents.
4
ADSTB[1:0]#
I/O
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising
and falling edge. Strobes are associated with signals as shown below.
4
AP[1:0]#
I/O
AP[1:0]# (Address Parity) are driven by the request initiator along with
ADS#, A[35:3]#, and the transaction type on the REQ[4:0]# pins. A correct
parity signal is high if an even number of covered signals are low and low if
an odd number of covered signals are low. This allows parity to be high
when all the covered signals are high. AP[1:0]# should connect the
appropriate pins of all system bus agents. The following table defines the
coverage model of these signals.
4
Request Signals
Subphase 1
Subphase 2
A[35:24]#
AP0#
AP1#
A[23:3]#
AP1#
AP0#
REQ[4:0]#
AP1#
AP0#
Signals
Associated Strobes
REQ[4:0]#, A[16:3]#
ADSTB0#
A[35:17]#
ADSTB1#
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相关代理商/技术参数 |
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| RK80546KG0802MMS L7ZF | 制造商:Intel 功能描述:MPU Xeon NetBurst 64-Bit 90nm 3GHz 604-Pin FCmPGA4 制造商:Intel 功能描述:XEON 3E GHZ,2M,800MHZ,FC MPGA4 - Trays |
| RK80546KG0881M S L7PF | 制造商:Intel 功能描述:INTEL XEON, 3.2DGHZ,1M,800MHZ,FC-MPGA4 - Trays |
| RK80546KG0882MMS L7ZE | 制造商:Intel 功能描述:XEON 3.2,2M,800MHZ,FC-MPGA4 - Trays |
| RK80546KG1041M | 制造商:Rochester Electronics LLC 功能描述:XEON 3.6GHZ,1M,800MHZ,FC MPGA4 - Bulk |
| RK80546KG1041M S L7PH | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU XEON 90NM 3.6GHZ 604PIN PGA - Trays |
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