- 您现在的位置：买卖IC网 > PDF目录1987 > AD9520-0BCPZ-REEL7 (Analog Devices Inc)IC CLOCK GEN 2.8GHZ VCO 64LFCSP PDF资料下载
参数资料
| 型号： | AD9520-0BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 37/80页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.8GHZ VCO 64LFCSP |
| 设计资源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 标准包装： | 750 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:12，2:24 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.95GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页当前第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页
AD9520-0
Data Sheet
Rev. A | Page 42 of 80
The VCO calibration clock divider is set as shown in Table 54
(Register 0x018[2:1]). The calibration divider divides the PFD
frequency (reference frequency divided by R) down to the
calibration clock. The calibration occurs at the PFD frequency
divided by the calibration divider setting. Lower VCO calibration
clock frequencies result in longer times for a calibration to be done.
The VCO calibration clock frequency is given by
fCAL_CLOCK = fREFIN/(R × cal_div)
where:
fREFIN is the frequency of the REFIN signal.
R is the value of the R counter.
cal_div is the division set for the VCO calibration divider
(Register 0x018[2:1]).
Choose a calibration divider such that the calibration frequency
is less than 6.25 MHz. Table 30 shows the appropriate value for
the calibration divider.
Table 30. VCO Calibration Divider Values for Different
Phase Detector Frequencies
PFD Rate (MHz)
Recommended VCO Calibration Divider
<12
Any
12 to 25
4, 8, 16
25 to 50
8, 16
50 to 100
16
The VCO calibration takes 4400 calibration clock cycles. Therefore,
the VCO calibration time in PLL reference clock cycles is given by
Time to Calibrate VCO =
4400 × R × cal_div PLL Reference Clock Cycles
Table 31. Example Time to Complete a VCO Calibration
with Different fREFIN Frequencies
fREFIN (MHz)
R Divider
PFD
Time to Calibrate VCO
100
1
100 MHz
88 s
10
1 MHz
8.8 ms
10
100
100 kHz
88 ms
A VCO calibration must be manually initiated, which allows for
flexibility in deciding what order to program registers and when
to initiate a calibration, instead of having it occur every time the
values of certain PLL registers change. For example, this allows
for the VCO frequency to be changed by small amounts without
having an automatic calibration occur each time; this should be
done with caution and only when the user knows the VCO control
voltage will not exceed the nominal best performance limits. For
example, a few 100 kHz steps are fine, but a few MHz may not be.
In addition, because the calibration procedure results in rapid
changes in the VCO frequency, the distribution section is
automatically placed in SYNC until the calibration is finished.
Therefore, this temporary loss of outputs must be expected.
A VCO calibration should be initiated in the following conditions:
After changing any of the PLL R, P, B, and A divider settings,
or after a change in the PLL reference clock frequency.
This, in effect, means any time a PLL register or reference
clock is changed such that a different VCO frequency results.
When system calibration is desired. The VCO is designed to
operate properly over extremes of temperature even when
it is first calibrated at the opposite extreme. However, a
VCO calibration can be initiated at any time, if desired.
ZERO DELAY OPERATION
Zero delay operation aligns the phase of the output clocks with
the phase of the external PLL reference input. There are two
zero delay modes on the AD9520: internal and external.
Internal Zero Delay Mode
The internal zero delay function of the AD9520 is achieved by
feeding the output of Channel Divider 0 back to the PLL N divider.
In Figure 49, the change in signal routing for internal zero delay
mode is shown in blue.
Set Register 0x01E[2:1] = 01b to select internal zero delay mode.
In the default internal zero delay mode, the output of Channel
Divider 0 is routed back to the PLL (N divider) through MUX3
and MUX1 (feedback path shown in blue in Figure 49). The PLL
synchronizes the phase/edge of the output of Channel Divider 0
with the phase/edge of the reference input. External zero delay
mode must be used if Channel Divider 1, Channel Divider 2, or
Channel Divider 3 is to be used for zero delay feedback. This is
accomplished by changing the value in Register 0x01E[4:3].
Because the channel dividers are synchronized to each other,
the outputs of the channel divider are synchronous with the
reference input. Both the R delay and the N delay inside the
PLL can be programmed to compensate for the propagation
delay from the output drivers and PLL components to minimize
the phase offset between the clock output and the reference
input to achieve zero delay.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9520-1BCPZ | IC CLOCK GEN 2.5GHZ VCO 64LFCSP |
| AD9520-2BCPZ | IC CLOCK GEN 2.2GHZ VCO 64LFCSP |
| AD9520-3BCPZ-REEL7 | IC CLOCK GEN 2GHZ VCO 64LFCSP |
| AD9520-4BCPZ-REEL7 | IC CLOCK GEN 1.6GHZ VCO 64LFCSP |
| AD9520-5BCPZ-REEL7 | IC CLOCK GEN EXT VCO 64LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9520-1 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO |
| AD9520-1/PCBZ | 功能描述:BOARD EVAL FOR AD9520-1 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9520-1BCPZ | 功能描述:IC CLOCK GEN 2.5GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9520-1BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2.5GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9520-2 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO |
发布紧急采购，3分钟左右您将得到回复。