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参数资料
| 型号： | AD9520-0BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 69/80页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.8GHZ VCO 64LFCSP |
| 设计资源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 标准包装： | 750 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:12，2:24 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.95GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
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Data Sheet
AD9520-0
Rev. A | Page 71 of 80
Table 55. Output Driver Control
Reg.
Addr.
(Hex)
Bits
Name
Description
0x0F0 7
OUT0 format
Selects the output type for OUT0.
0: LVPECL (default).
1: CMOS.
[6:5]
OUT0 CMOS
configuration
Sets the CMOS output configuration for OUT0 when Register 0x0F0[7] = 1b.
Bits[6:5]
OUT0A
OUT0B
00
01
10
11 (default)
Tristate
On
Tristate
On
Tristate
On
[4:3]
OUT0 polarity
Sets the output polarity for OUT0.
Bit 7
Bit 4
Bit 3
Output Type
OUT0A
OUT0B
0 (default)
0
1
X
0 (default)
0
1
0 (default)
1
0
1
0
1
LVPECL
CMOS
Noninverting
Inverting
Noninverting
Inverting
Noninverting
Inverting
Noninverting
Inverting
Noninverting
[2:1]
OUT0 LVPECL
differential voltage
Sets the LVPECL output differential voltage (VOD).
Bit 2
Bit 1
VOD (mV)
0
1 (default)
1
0
1
0 (default)
1
400
600
780
960
0
OUT0 LVPECL
power-down
LVPECL power-down.
0: normal operation (default).
1: safe power-down.
0x0F1 [7:0]
OUT1 control
This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0.
0x0F2 [7:0]
OUT2 control
This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0.
0x0F3 [7:0]
OUT3 control
This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0.
0x0F4 [7:0]
OUT4 control
This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0.
0x0F5 [7:0]
OUT5 control
This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0.
0x0F6 [7:0]
OUT6 control
This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0.
0x0F7 [7:0]
OUT7 control
This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0.
0x0F8 [7:0]
OUT8 control
This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0.
0x0F9 [7:0]
OUT9 control
This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0.
0x0FA [7:0]
OUT10 control
This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0.
0x0FB [7:0]
OUT11 control
This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0.
0x0FC 7
CSDLD en OUT7
OUT7 is enabled only if the CSDLD signal is high.
Bit 7
CSDLD
Signal
OUT7 Enable Status
0
1
0
1
Not affected by CSDLD signal (default).
Asynchronous power-down.
Asynchronously enables OUT7 if not powered down by other settings. For this feature, use
current source digital lock detect and set the enable LD pin comparator bit (Register 0x01D[3]).
6
CSDLD en OUT6
OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
5
CSDLD en OUT5
OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
4
CSDLD en OUT4
OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
3
CSDLD en OUT3
OUT3 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
2
CSDLD en OUT2
OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
1
CSDLD en OUT1
OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0
CSDLD en OUT0
OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0x0FD [7:4]
Unused
Unused.
3
CSDLD en OUT11
OUT11 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
2
CSDLD en OUT10
OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
1
CSDLD en OUT9
OUT9 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0
CSDLD en OUT8
OUT8 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9520-1 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO |
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| AD9520-1BCPZ | 功能描述:IC CLOCK GEN 2.5GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
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| AD9520-2 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO |
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