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参数资料
| 型号： | AD9520-0BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 55/80页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.8GHZ VCO 64LFCSP |
| 设计资源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 标准包装： | 750 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:12，2:24 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.95GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
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Data Sheet
AD9520-0
Rev. A | Page 59 of 80
PROGRAMMING THE EEPROM BUFFER SEGMENT
The EEPROM buffer segment is a register space on the AD9520.
The user can specify which groups of registers are stored to the
EEPROM during EEPROM programming. Note that programming
this register space is optional. The default power-up values for the
EEPROM buffer segment allow storage of all the AD9520 register
values from Register 0x000 to Register 0x231 to the EEPROM.
As an example, a user might want to load only the output driver
settings from the EEPROM without disturbing the PLL register
settings currently stored in the AD9520. The user can alter the
EEPROM buffer segment to include only the registers that apply
to the output drivers and exclude the registers that apply to the
PLL configuration.
There are two parts to the EEPROM buffer segment: register
section definition groups and operational codes. Table 48 shows
an example of the EEPROM buffer segment.
Register Section Definition Group
Note that the AD9520 register map is noncontiguous, and the
EEPROM is only 512 bytes long. The register section definition
group tells the EEPROM controller how the AD9520 register map
is segmented. Each register section definition group contains the
starting address and number of bytes to be written to EEPROM.
The register section definition group defines a continuous register
section for the EEPROM profile. It consists of three bytes. The first
byte defines how many continuous register bytes are in this group.
If the user writes 0x000 to the first byte, it means that there is
only one byte in this group. If the user writes 0x001, it means
that there are two bytes in this group. The maximum number of
registers in one group is 128. The next two bytes are the low
byte and high byte, respectively, of the 16-bit memory address
of the first register in this group.
Operational Codes
There are three operational codes: IO_UPDATE, end-of-data, and
pseudo-end-of-data. It is important that the EEPROM buffer
segment always have either an end-of-data or a pseudo-end-of-data
operational code and that an IO_UPDATE operational code appear
at least once before the end-of-data operational code.
IO_UPDATE (Operational Code 0x80)
The EEPROM controller uses this operational code to generate
an IO_UPDATE signal to update the active control register
bank from the buffer register bank during the download process.
At a minimum, there should be at least one IO_UPDATE
operational code after the end of the final register section definition
group. This code is needed so that at least one IO_UPDATE occurs
after all of the AD9520 registers are loaded when the EEPROM
is read. If this operational code is absent during a write to the
EEPROM, the register values loaded from the EEPROM are not
transferred to the active register space, and these values do not take
effect after they are loaded from the EEPROM to the AD9520.
End-of-Data (Operational Code 0xFF)
The EEPROM controller uses this operational code to terminate
the data transfer process between EEPROM and the control
register during the upload and download process. The last item
appearing in the EEPROM buffer segment should be either this
operational code or the pseudo-end-of-data operational code.
Pseudo-End-of-Data (Operational Code 0xFE)
The AD9520 EEPROM buffer segment has 23 bytes that can
contain up to seven register section definition groups. If the
user wants to define more than seven register section definition
groups, the pseudo-end-of-data operational code can be used.
During the upload process, when the EEPROM controller
receives the pseudo-end-of-data operational code, it halts the
data transfer process, clears the REG2EEPROM bit, and enables
the AD9520 serial port. The user can then program the EEPROM
buffer segment again and reinitiate the data transfer process by
setting the REG2EEPROM bit (Register 0xB03[0]) to 1b and the
IO_UPDATE bit (Register 0x232[0]) to 1b. The internal IC master
then begins writing to the EEPROM starting from the EEPROM
address held from the last writing.
This sequence provides the user with more discrete instructions
that can be written to the EEPROM than would otherwise be
possible due to the limited size of the EEPROM buffer segment.
It also allows for the same register to be written multiple times
with a different value each time.
Table 48. Example of the EEPROM Buffer Segment
Reg. Addr. (Hex)
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Start EEPROM Buffer Segment
0xA00
0
Number of bytes [6:0] of the first group of registers
0xA01
Address [15:8] of the first group of registers
0xA02
Address [7:0] of the first group of registers
0xA03
0
Number of bytes [6:0] of the second group of registers
0xA04
Address [15:8] of the second group of registers
0xA05
Address [7:0] of the second group of registers
0xA06
0
Number of bytes [6:0] of the third group of registers
0xA07
Address [15:8] of the third group of registers
0xA08
Address [7:0] of the third group of registers
0xA09
IO_UPDATE operational code (0x80)
0xA0A
End-of-data operational code (0xFF)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9520-1 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO |
| AD9520-1/PCBZ | 功能描述:BOARD EVAL FOR AD9520-1 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9520-1BCPZ | 功能描述:IC CLOCK GEN 2.5GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9520-1BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2.5GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9520-2 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO |
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