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型号： AD9520-0BCPZ-REEL7
厂商： Analog Devices Inc
文件页数： 67/80页
文件大小： 0K
描述： IC CLOCK GEN 2.8GHZ VCO 64LFCSP
设计资源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
标准包装： 750
类型： 时钟发生器，扇出配送
PLL： 是
输入： CMOS，LVDS，LVPECL
输出： CMOS，LVPECL
电路数： 1
比率 - 输入:输出： 2:12，2:24
差分 - 输入:输出： 是/是
频率 - 最大： 2.95GHz
除法器/乘法器： 是/无
电源电压： 3.135 V ~ 3.465 V
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 64-VFQFN 裸露焊盘，CSP
供应商设备封装： 64-LFCSP-VQ（9x9）
包装： 带卷 (TR)
Data Sheet
AD9520-0
Rev. A | Page 7 of 80
CLOCK INPUTS
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CLOCK INPUTS (CLK, CLK)
Differential input
Input Frequency
01
2.4
GHz
High frequency distribution (VCO divider)
01
2.0
GHz
Distribution only (VCO divider bypassed); this is the
frequency range supported by the channel divider for
all divide ratios except divide-by-17 and divide-by-3
01
1.6
GHz
Distribution only (VCO divider bypassed); this is the
frequency range supported by all channel divider ratios
Input Sensitivity, Differential
150
mV p-p
Measured at 2.4 GHz; jitter performance is improved with
slew rates > 1 V/ns; the input sensitivity is sufficient for
ac-coupled LVDS and LVPECL signals
Input Level, Differential
2
V p-p
Larger voltage swings can turn on the protection
diodes and can degrade jitter performance
Input Common-Mode Voltage, VCM
1.3
1.57
1.8
V
Self-biased; enables ac coupling
Input Common-Mode Range, VCMR
1.3
1.8
V
With 200 mV p-p signal applied; dc-coupled
Input Sensitivity, Single-Ended
150
mV p-p
CLK ac-coupled; CLK ac-bypassed to RF ground
Input Resistance
3.9
4.7
5.7
k
Self-biased
Input Capacitance
2
pF
1
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL CLOCK OUTPUTS
Termination = 50 to VS_DRV 2 V
OUT0, OUT1, OUT2, OUT3, OUT4,
OUT5, OUT6, OUT7, OUT8,
OUT9, OUT10, OUT11
Differential (OUT, OUT)
Output Frequency, Maximum
2400
MHz
Using direct to output (see Figure 20); higher frequencies
are possible, but the resulting amplitude does not meet
the VOD specification; the maximum output frequency is
limited by either the maximum VCO frequency or the
frequency at the CLK inputs, depending on the AD9520
configuration
Output High Voltage, VOH
VS_DRV 1.07
VS_DRV 0.96
VS_DRV 0.84
V
Output Low Voltage, VOL
VS_DRV 1.95
VS_DRV 1.79
VS_DRV 1.64
V
Output Differential Voltage, VOD
660
820
950
mV
VOH VOL for each leg of a differential pair for default
amplitude setting with the driver not toggling; the peak-
to-peak amplitude measured using a differential probe
across the differential pair with the driver toggling is
roughly 2× these values (see Figure 20 for variation over
frequency)
CMOS CLOCK OUTPUTS
OUT0A, OUT0B, OUT1A, OUT1B,
OUT2A, OUT2B, OUT3A, OUT3B,
OUT4A, OUT4B, OUT5A, OUT5B,
OUT6A, OUT6B, OUT7A, OUT7B,
OUT8A, OUT8B, OUT9A, OUT9B,
OUT10A, OUT10B, OUT11A,
OUT11B
Single-ended; termination = 10 pF
Output Frequency
250
MHz
See Figure 21
Output Voltage High, VOH
VS 0.1
V
1 mA load, VS_DRV = 3.3 V/2.5 V
Output Voltage Low, VOL
0.1
V
1 mA load, VS_DRV = 3.3 V/2.5 V
Output Voltage High, VOH
2.7
V
10 mA load, VS_DRV = 3.3 V
Output Voltage Low, VOL
0.5
V
10 mA load, VS_DRV = 3.3 V
Output Voltage High, VOH
1.8
V
10 mA load, VS_DRV = 2.5 V
Output Voltage Low, VOL
0.6
V
10 mA load, VS_DRV = 2.5 V
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相关代理商/技术参数
参数描述
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AD9520-1BCPZ 功能描述:IC CLOCK GEN 2.5GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR)
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AD9520-2 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO
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