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| 型号： | AD9520-0BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 46/80页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.8GHZ VCO 64LFCSP |
| 设计资源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 标准包装： | 750 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:12，2:24 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.95GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
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AD9520-0
Data Sheet
Rev. A | Page 50 of 80
Hardware Reset via the RESET Pin
RESET, a hard reset (an asynchronous hard reset is executed by
briefly pulling RESET low), restores the chip either to the setting
stored in the EEPROM (the EEPROM pin = 1b) or to the on-chip
setting (the EEPROM pin = 0b). A hard reset also executes
a SYNC operation, bringing the outputs into phase alignment
according to the default settings. When the EEPROM is inactive
(the EEPROM pin = 0b), it takes ~2 s for the outputs to begin
toggling after RESET is issued. When the EEPROM is active
(the EEPROM pin = 1b), it takes ~20 ms for the outputs to toggle
after RESET is brought high.
Soft Reset via the Serial Port
The serial port control register allows for a soft reset by setting
Bit 2 and Bit 5 in Register 0x000. The function of this register is
determined by the state of the EEPROM pin.
When Bit 2 and Bit 5 are set and the EEPROM pin is high, the chip
is restored to the settings saved in the EEPROM. When Bit 2 and
Bit 5 are set and the EEPROM pin is low, the chip is restored to
the on-chip defaults.
Except for the self-clearing bits, Bit 2 and Bit 5, Register 0x000
retains its previous value prior to reset. During the internal reset,
the outputs hold static. However, the self-clearing operation does
not complete until an additional serial port SCLK cycle occurs,
and the AD9520 is held in reset until that happens.
Soft Reset to Settings in EEPROM when EEPROM Pin = 0b
via the Serial Port
If the EEPROM pin is low, the serial port control register allows
the chip to be reset to settings in EEPROM via Register 0xB02[1].
(Bit 1 is self-clearing.) This bit does not have any effect when the
EEPROM pin is high. It takes ~20 ms for the outputs to begin
toggling after the SOFT_EEPROM register is cleared.
POWER-DOWN MODES
Chip Power-Down via PD
The AD9520 can be put into a power-down condition by
pulling the PD pin low. Power-down turns off most of the
functions and currents inside the AD9520. The chip remains
in this power-down state until PD is brought back to logic high.
When taken out of power-down mode, the AD9520 returns to
the settings programmed into its registers prior to the power-
down, unless the registers are changed by new programming
while the PD pin is held low.
Powering down the chip shuts down the currents on the chip,
except for the bias current necessary to maintain the LVPECL
outputs in a safe shutdown mode. The LVPECL bias currents are
needed to protect the LVPECL output circuitry from damage that
can be caused by certain termination and load configurations
when tristated. Because this is not a complete power-down, it
can be called sleep mode. The AD9520 contains special circuitry to
prevent runt pulses on the outputs when the chip is entering or
exiting sleep mode.
When the AD9520 is in a PD power-down, the chip is in the
following state:
The PLL is off (asynchronous power-down).
The VCO is off.
The CLK input buffer is off, but the CLK input dc bias
circuit is on.
In differential mode, the reference input buffer is off, but
the dc bias circuit is still on.
In singled-ended mode, the reference input buffer is off,
and the dc bias circuit is off.
All dividers are off.
All CMOS outputs are tristated.
All LVPECL outputs are in safe off mode.
The serial control port is active, and the chip responds to
commands.
PLL Power-Down
The PLL section of the AD9520 can be selectively powered down.
There are two PLL power-down modes set by Register 0x010[1:0]:
asynchronous and synchronous.
In asynchronous power-down mode, the device powers down as
soon as the registers are updated. In synchronous power-down
mode, the PLL power-down is gated by the charge pump to
prevent unwanted frequency jumps. The device goes into power-
down on the occurrence of the next charge pump event after the
registers are updated.
Distribution Power-Down
The distribution section can be powered down by writing
Register 0x230[1] = 1b, which turns off the bias to the distribution
section. If the LVPECL power-down mode is in normal operation
(Register 0x230[1] = 0b), it is possible for a low impedance load
on that LVPECL output to draw significant current during this
power-down. If the LVPECL power-down mode is set to 1b, the
LVPECL output is not protected from reverse bias and can be
damaged under certain termination conditions.
Individual Clock Output Power-Down
Any of the clock distribution outputs can be powered down
into safe power-down mode by individually writing to the
appropriate registers. The register map details the individual
power-down settings for each output. These settings are found
in Bit 0 of Register 0x0F0 to Register 0x0FB.
Individual Clock Channel Power-Down
Any of the clock distribution channels can be powered down
individually by writing to the appropriate registers. Powering
down a clock channel is similar to powering down an individual
driver, but it saves more power because the dividers are also
powered down. Powering down a clock channel also automatically
powers down the drivers connected to it. The register map details
the individual power-down settings for each output channel.
These settings are found in Bit 2 of Register 0x192, Register 0x195,
Register 0x198, and Register 0x19B.
相关PDF资料 |
PDF描述 |
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| AD9520-1BCPZ | IC CLOCK GEN 2.5GHZ VCO 64LFCSP |
| AD9520-2BCPZ | IC CLOCK GEN 2.2GHZ VCO 64LFCSP |
| AD9520-3BCPZ-REEL7 | IC CLOCK GEN 2GHZ VCO 64LFCSP |
| AD9520-4BCPZ-REEL7 | IC CLOCK GEN 1.6GHZ VCO 64LFCSP |
| AD9520-5BCPZ-REEL7 | IC CLOCK GEN EXT VCO 64LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9520-1 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO |
| AD9520-1/PCBZ | 功能描述:BOARD EVAL FOR AD9520-1 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9520-1BCPZ | 功能描述:IC CLOCK GEN 2.5GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9520-1BCPZ-REEL7 | 功能描述:IC CLOCK GEN 2.5GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9520-2 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO |
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