参数资料
型号: ADE7878ACPZ
厂商: Analog Devices Inc
文件页数: 57/100页
文件大小: 0K
描述: IC ENERGY METERING 3PH 40LFCSP
标准包装: 1
输入阻抗: 400 千欧
测量误差: 0.2%
电压 - 高输入/输出: 2.4V
电压 - 低输入/输出: 0.4V
电源电压: 2.4 V ~ 3.7 V
测量仪表类型: 3 相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘,CSP
供应商设备封装: 40-LFCSP-WQ(6x6)
包装: 托盘
xVA =
V I 1
× PMAX × 4
DataSheet
APPARENT POWER CALCULATION
Apparent power is defined as the maximum power that can be
delivered to a load. One way to obtain the apparent power is by
multiplying the voltage rms value by the current rms value (also
called the arithmetic apparent power)
ADE7854/ADE7858/ADE7868/ADE7878
The ADE7854 / ADE7858 / ADE7868 / ADE7878 store the instan-
taneous phase apparent powers into the AVA, BVA, and CVA
registers. Their expression is
× (40)
V FS I FS 2
S = V rms × I rms
(39)
where:
where:
S is the apparent power.
V rms and I rms are the rms voltage and current, respectively.
The ADE7854 / ADE7858 / ADE7868 / ADE7878 compute the
arithmetic apparent power on each phase. Figure 73 illustrates
the signal processing in each phase for the calculation of the
apparent power in the ADE78xx . Because V rms and I rms con-
tain all harmonic information, the apparent power computed by
the ADE78xx is total apparent power. The ADE7878 does not
compute fundamental apparent power because it does not measure
the rms values of the fundamental voltages and currents.
V, I are the rms values of the phase voltage and current.
V FS , I FS are the rms values of the phase voltage and current when
the ADC inputs are at full scale.
PMAX = 33,516,139, the instantaneous power computed when
the ADC inputs are at full scale and in phase.
The xVA[23:0] waveform registers may be accessed using
various serial ports. Refer to the Waveform Sampling Mode
section for more details.
The ADE7854 / ADE7858 / ADE7868 / ADE7878 can compute the
apparent power in an alternative way by multiplying the phase
rms current by an rms voltage introduced externally. See the
Apparent Power Calculation Using VNOM section for details.
AIRMS
AVAGAIN
ACCUMULATOR
AVAHR[31:0]
32-BIT REGISTER
AVRMS
AVA
VATHR[47:0]
2 4
DIGITAL SIGNAL PROCESSOR
Figure 73. Apparent Power Data Flow and Apparent Energy Accumulation
Rev. H | Page 57 of 100
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