参数资料
型号: ADE7878ACPZ
厂商: Analog Devices Inc
文件页数: 92/100页
文件大小: 0K
描述: IC ENERGY METERING 3PH 40LFCSP
标准包装: 1
输入阻抗: 400 千欧
测量误差: 0.2%
电压 - 高输入/输出: 2.4V
电压 - 低输入/输出: 0.4V
电源电压: 2.4 V ~ 3.7 V
测量仪表类型: 3 相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘,CSP
供应商设备封装: 40-LFCSP-WQ(6x6)
包装: 托盘
ADE7854/ADE7858/ADE7868/ADE7878
Data Sheet
8:6
PGA3[2:0]
000
Phase voltages gain selection.
000: gain = 1.
001: gain = 2.
010: gain = 4.
011: gain = 8.
100: gain = 16.
101, 110, 111: reserved. When set, the ADE7854 / ADE7858 / ADE7868 / ADE7878 behave
like PGA3[2:0] = 000.
15:9
Reserved
000 0000
Reserved. These bits do not manage any functionality.
Table 45. CFMODE Register (Address 0xE610)
Bit
Location
2:0
Bit Mnemonic
CF1SEL[2:0]
Default Value
000
Description
000: the CF1 frequency is proportional to the sum of total active powers on each phase
identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register.
001: the CF1 frequency is proportional to the sum of total reactive powers on each phase
identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register. This condition does not
have any consequence for the ADE7854 .
010: the CF1 frequency is proportional to the sum of apparent powers on each phase
identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register.
011: the CF1 frequency is proportional to the sum of fundamental active powers on each
phase identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register. This condition does
not have any consequence for the ADE7854 , ADE7858 , and ADE7868 .
100: the CF1 frequency is proportional to the sum of fundamental reactive powers on each
phase identified by Bits[2:0] (TERMSEL1[x]) in the COMPMODE register. This condition does
not have any consequence for the ADE7854 , ADE7858 , and ADE7868 .
101, 110, 111: reserved. When set, the CF1 signal is not generated.
5:3
CF2SEL[2:0]
001
000: the CF2 frequency is proportional to the sum of total active powers on each phase
identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register.
001: the CF2 frequency is proportional to the sum of total reactive powers on each phase
identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register. This condition does not
have any consequence for the ADE7854 .
010: the CF2 frequency is proportional to the sum of apparent powers on each phase
identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register.
011: the CF2 frequency is proportional to the sum of fundamental active powers on each
phase identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register. This condition does
not have any consequence for the ADE7854 , ADE7858 , and ADE7868 .
100: the CF2 frequency is proportional to the sum of fundamental reactive powers on each
phase identified by Bits[5:3] (TERMSEL2[x]) in the COMPMODE register. This condition does
not have any consequence for the ADE7854 , ADE7858 , and ADE7868 .
101,110,111: reserved. When set, the CF2 signal is not generated.
8:6
CF3SEL[2:0]
010
000: the CF3 frequency is proportional to the sum of total active powers on each phase
identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register.
001: the CF3 frequency is proportional to the sum of total reactive powers on each phase
identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register. This condition does not
have any consequence for the ADE7854 .
010: the CF3 frequency is proportional to the sum of apparent powers on each phase
identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register.
011: CF3 frequency is proportional to the sum of fundamental active powers on each phase
identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register. This condition does not
have any consequence for the ADE7854 , ADE7858 , and ADE7868 .
100: CF3 frequency is proportional to the sum of fundamental reactive powers on each
phase identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register. This condition does
not have any consequence for the ADE7854 , ADE7858 , and ADE7868 .
101,110,111: reserved. When set, the CF3 signal is not generated.
9
CF1DIS
1
When this bit is set to 1, the CF1 output is disabled. The respective digital to frequency
converter remains enabled even if CF1DIS = 1.
When this bit is set to 0, the CF1 output is enabled.
Rev. H| Page 92 of 100
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