参数资料
型号: ADE7878ACPZ
厂商: Analog Devices Inc
文件页数: 76/100页
文件大小: 0K
描述: IC ENERGY METERING 3PH 40LFCSP
标准包装: 1
输入阻抗: 400 千欧
测量误差: 0.2%
电压 - 高输入/输出: 2.4V
电压 - 低输入/输出: 0.4V
电源电压: 2.4 V ~ 3.7 V
测量仪表类型: 3 相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘,CSP
供应商设备封装: 40-LFCSP-WQ(6x6)
包装: 托盘
ADE7854/ADE7858/ADE7868/ADE7878
Figure 96. ADE7878 Top Layer Printed Circuit Board
The exposed pad of the ADE7878 is soldered to an equivalent
pad on the PCB. The AGND and DGND traces of the ADE7878
are then routed directly into the PCB pad.
The bottom layer is composed mainly of a ground plane
surrounding as much as possible the crystal traces.
Data Sheet
shown in Figure 98. CL 1 and CL 2 denote the capacitances of the
ceramic capacitors attached to the crystal pins, whereas CP 1 and
CP 2 denote the parasitic capacitances on those pins.
The recommended typical value of total capacitance at each
clock pin, CLKIN and CLKOUT, is 24 pF, which means that
Total Capacitance = CP 1 + CL 1 = CP 2 + CL 2 = 24 pF
Crystal manufacturer data sheets specify the load capacitance
value. A total capacitance of 24 pF, per clock pin, is recommended;
therefore, select a crystal with a 12 pF load capacitance. In
addition, when selecting the ceramic capacitors, CL 1 and CL 2 ,
the parasitic capacitances, CP 1 and CP 2 , on the crystal pins of
the IC must be taken into account. Thus, the values of CL 1 and
CL 2 must be based on the following expression:
CL 1 = CL 2 = 2 × Crystal Load Capacitance ? CP 1
where CP 1 = CP 2 .
For example, if a 12 pF crystal is chosen and the parasitic
capacitances on the clock pins are CP 1 = CP 2 = 2 pF, the ceramic
capacitors that must be used in the crystal circuit are CL 1 = CL 2
= 22 pF.
The Evaluation Board EVAL-ADE7878EBZ uses the crystal
VM6-1D11C12-TR-16.384MHZ (maximum drive level 1 mW;
maximum ESR 20 Ω; load capacitance 12 pF). It is recommended
that the same crystal, or a crystal with similar specifications, be
selected. Lower values of ESR and load capacitance and higher
values of drive level capability of the crystal are preferable.
It is also recommended that a 5 MΩ resistor be attached in
parallel to the crystal, as shown in Figure 98.
CL 2
CLKIN
CP 2
GND
ADE78xx IC
5M ?
16.384MHz CRYSTAL
CP 1
CLKOUT
GND
CL 1
Figure 98. Crystal Circuit
ADE7878 EVALUATION BOARD
An evaluation board built upon the ADE7878 configuration
supports all ADE7854 , ADE7858 , ADE7868 , and ADE7878
components. Visit www.analog.com/ADE7878 for details.
Figure 97. ADE7878 Bottom Layer Printed Circuit Board
DIE VERSION
CRYSTAL CIRCUIT
The register named version identifies the version of the die. It is
an 8-bit, read-only version register located at Address 0xE707.
A digital clock signal of 16.384 MHz can be provided to the
CLKIN pin of the ADE7854 / ADE7858 / ADE7868 / ADE7878 .
Alternatively, attach a crystal of the specified frequency, as
Rev. H | Page 76 of 100
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