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| 型号： | ADE7878ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 88/100页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METERING 3PH 40LFCSP |
| 标准包装： | 1 |
| 输入阻抗： | 400 千欧 |
| 测量误差： | 0.2% |
| 电压 - 高输入/输出： | 2.4V |
| 电压 - 低输入/输出： | 0.4V |
| 电源电压： | 2.4 V ~ 3.7 V |
| 测量仪表类型： | 3 相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-WQ（6x6） |
| 包装： | 托盘 |
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ADE7854/ADE7858/ADE7868/ADE7878
Table 39. MASK0 Register (Address 0xE50A)
Data Sheet
Bit
Location
0
Bit Mnemonic
AEHF
Default Value
0
Description
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the total active
energy registers (AWATTHR, BWATTHR, or CWATTHR) changes.
1
FAEHF
0
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the fundamental
active energy registers (AFWATTHR, BFWATTHR, or CFWATTHR) changes. Setting this bit to1
2
REHF
0
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the total reactive
energy registers (AVARHR, BVARHR, CVARHR) changes. Setting this bit to1 does not have any
3
FREHF
0
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the fundamental
reactive energy registers (AFVARHR, BFVARHR, or CFVARHR) changes. Setting this bit to1
4
VAEHF
0
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the apparent
energy registers (AVAHR, BVAHR, or CVAHR) changes.
5
LENERGY
0
When this bit is set to 1, in line energy accumulation mode, it enables an interrupt at the end
of an integration over an integer number of half line cycles set in the LINECYC register.
6
7
8
9
10
REVAPA
REVAPB
REVAPC
REVPSUM1
REVRPA
0
0
0
0
0
When this bit is set to 1, it enables an interrupt when the Phase A active power identified by
Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental) changes sign.
When this bit is set to 1, it enables an interrupt when the Phase B active power identified by
Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental) changes sign.
When this bit is set to 1, it enables an interrupt when the Phase C active power identified by
Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental) changes sign.
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF1
datapath changes sign.
When this bit is set to 1, it enables an interrupt when the Phase A reactive power identified
by Bit 7 (REVRPSEL) in the ACCMODE register (total or fundamental) changes sign. Setting
11
REVRPB
0
When this bit is set to 1, it enables an interrupt when the Phase B reactive power identified
by Bit 7 (REVRPSEL) in the ACCMODE register (total or fundamental) changes sign. Setting
12
REVRPC
0
When this bit is set to 1, it enables an interrupt when the Phase C reactive power identified
by Bit 7 (REVRPSEL) in the ACCMODE register (total or fundamental) changes sign. Setting
13
14
REVPSUM2
CF1
0
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF2
datapath changes sign.
When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at the
CF1 pin, that is, an active low pulse is generated. The interrupt can be enabled even if the
CF1 output is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of
power used at the CF1 pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register
15
16
CF2
CF3
When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at CF2
pin, that is, an active low pulse is generated. The interrupt may be enabled even if the CF2
output is disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of power
used at the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE register (see Table 45).
When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF3
pin, that is, an active low pulse is generated. The interrupt may be enabled even if the CF3
output is disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of power
used at the CF3 pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register (see Table 45).
17
DREADY
0
When this bit is set to 1, it enables an interrupt when all periodical (at 8 kHz rate) DSP
computations finish.
18
REVPSUM3
0
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF3
datapath changes sign.
31:19
Reserved
00 0000 0000
Reserved. These bits do not manage any functionality.
0000
Rev. H| Page 88 of 100
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| ADE7878ACPZ | 制造商:Analog Devices 功能描述:IC MULTIFUNCTION ENERGY METERING LFCSP40 |
| ADE7878ACPZ-RL | 功能描述:IC ENERGY METERING 3PH 40LFCSP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
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