参数资料
型号: ADE7878ACPZ
厂商: Analog Devices Inc
文件页数: 94/100页
文件大小: 0K
描述: IC ENERGY METERING 3PH 40LFCSP
标准包装: 1
输入阻抗: 400 千欧
测量误差: 0.2%
电压 - 高输入/输出: 2.4V
电压 - 低输入/输出: 0.4V
电源电压: 2.4 V ~ 3.7 V
测量仪表类型: 3 相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘,CSP
供应商设备封装: 40-LFCSP-WQ(6x6)
包装: 托盘
ADE7854/ADE7858/ADE7868/ADE7878
Bit
Data Sheet
Location
7
Bit Mnemonic
SUM2SIGN
Default Value
0
Description
0: if the sum of all phase powers in the CF2 datapath is positive.
1: if the sum of all phase powers in the CF2 datapath is negative. Phase powers in the CF2
datapath are identified by Bits[5:3] (TERMSEL2[x]) of the COMPMODE register and by
Bits[5:3] (CF2SEL[x]) of the CFMODE register.
8
SUM3SIGN
0
0: if the sum of all phase powers in the CF3 datapath is positive.
1: if the sum of all phase powers in the CF3 datapath is negative. Phase powers in the CF3
datapath are identified by Bits[8:6] (TERMSEL3[x]) of the COMPMODE register and by
Bits[8:6] (CF3SEL[x]) of the CFMODE register.
15:9
Reserved
000 0000
Reserved. These bits are always 0.
Table 48. C ONFIG     Registe r (Address 0xE618)
Bit
Location
0
Bit Mnemonic
INTEN
Default Value
0
Description
Integrator enable. When this bit is set to 1, the internal digital integrator is enabled for use in
meters utilizing Rogowski coils on all 3-phase and neutral current inputs.
When this bit is cleared to 0, the internal digital integrator is disabled.
2:1
3
Reserved
SWAP
00
0
Reserved. These bits do not manage any functionality.
When this bit is set to 1, the voltage channel outputs are swapped with the current channel
outputs. Thus, the current channel information is present in the voltage channel registers
and vice versa.
4
5
6
MOD1SHORT
MOD2SHORT
HSDCEN
0
0
0
When this bit is set to 1, the voltage channel ADCs behave as if the voltage inputs were put
to ground.
When this bit is set to 1, the current channel ADCs behave as if the voltage inputs were put
to ground.
When this bit is set to 1, the HSDC serial port is enabled and HSCLK functionality is chosen at
CF3/HSCLK pin.
When this bit is cleared to 0, HSDC is disabled and CF3 functionality is chosen at CF3/HSCLK pin.
7
9:8
SWRST
VTOIA[1:0]
0
00
When this bit is set to 1, a software reset is initiated.
These bits decide what phase voltage is considered together with Phase A current in the
power path.
00 = Phase A voltage.
01 = Phase B voltage.
10 = Phase C voltage.
11 = reserved. When set, the ADE7854 / ADE7858 / ADE7868 / ADE7878 behave like VTOIA[1:0] =
00.
11:10
VTOIB[1:0]
00
These bits decide what phase voltage is considered together with Phase B current in the
power path.
00 = Phase B voltage.
01 = Phase C voltage.
10 = Phase A voltage.
11 = reserved. When set, the ADE7854 / ADE7858 / ADE7868 / ADE7878 behave like VTOIB[1:0] =
00.
13:12
VTOIC[1:0]
00
These bits decide what phase voltage is considered together with Phase C current in the
power path.
00 = Phase C voltage.
01 = Phase A voltage.
10 = Phase B voltage.
11 = reserved. When set, the ADE7854 / ADE7858 / ADE7868 / ADE7878 behave like VTOIC[1:0] =
00.
15:14
Reserved
0
Reserved. These bits do not manage any functionality.
Rev. H| Page 94 of 100
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