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| 型号： | ADE7878ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 81/100页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METERING 3PH 40LFCSP |
| 标准包装： | 1 |
| 输入阻抗： | 400 千欧 |
| 测量误差： | 0.2% |
| 电压 - 高输入/输出： | 2.4V |
| 电压 - 低输入/输出： | 0.4V |
| 电源电压： | 2.4 V ~ 3.7 V |
| 测量仪表类型： | 3 相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-WQ（6x6） |
| 包装： | 托盘 |
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Data Sheet
ADE7854/ADE7858/ADE7868/ADE7878
Register
Bit
Bit Length During
Default
Address
0x43A3
0x43A4
0x43A5
0x43A6
0x43A7
Name
AFVARGAIN
AFVAROS
BFVARGAIN
BFVAROS
CFVARGAIN
R/W 1
R/W
R/W
R/W
R/W
R/W
Length
24
24
24
24
24
Communication 2
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
32 ZPSE
Type 3
S
S
S
S
S
Value
0x000000
0x000000
0x000000
0x000000
0x000000
Description
Phase A fundamental reactive power gain
adjust ( ADE7878 only).
Phase A fundamental reactive power
offset adjust ( ADE7878 only).
Phase B fundamental reactive power gain
adjust ( ADE7878 only).
Phase B fundamental reactive power
offset adjust ( ADE7878 only).
Phase C fundamental reactive power gain
adjust ( ADE7878 only).
0x43A8
0x43A9
CFVAROS
VATHR1
R/W
R/W
24
24
32 ZPSE
32 ZP
S
U
0x000000
0x000000
Phase C fundamental reactive power
offset adjust ( ADE7878 only).
Most significant 24 bits of VATHR[47:0]
threshold used in phase apparent power
datapath.
0x43AA
VATHR0
R/W
24
32 ZP
U
0x000000
Less significant 24 bits of VATHR[47:0]
threshold used in phase apparent power
datapath.
0x43AB
WTHR1
R/W
24
32 ZP
U
0x000000
Most significant 24 bits of WTHR[47:0]
threshold used in phase total/fundamental
active power datapath.
0x43AC
0x43AD
WTHR0
VARTHR1
R/W
R/W
24
24
32 ZP
32 ZP
U
U
0x000000
0x000000
Less significant 24 bits of WTHR[47:0]
threshold used in phase total/fundamental
active power datapath.
Most significant 24 bits of VARTHR[47:0]
threshold used in phase total/fundamental
0x43AE
VARTHR0
R/W
24
32 ZP
U
0x000000
Less significant 24 bits of VARTHR[47:0]
threshold used in phase total/fundamental
0x43AF
0x43B0
Reserved
VANOLOAD
N/A 4
R/W
N/A 4
24
N/A 4
32 ZPSE
N/A 4
S
0x000000
0x0000000
This memory location should be kept at
0x000000 for proper operation.
No load threshold in the apparent power
datapath.
0x43B1
0x43B2
APNOLOAD
VARNOLOAD
R/W
R/W
24
24
32 ZPSE
32 ZPSE
S
S
0x0000000
0x0000000
No load threshold in the total/fundamental
active power datapath.
No load threshold in the total/fundamental
reactive power datapath. Location
0x43B3
VLEVEL
R/W
24
32 ZPSE
S
0x000000
Register used in the algorithm that
computes the fundamental active and
reactive powers ( ADE7878 only).
0x43B4
0x43B5
Reserved
DICOEFF
N/A 4
R/W
N/A 4
24
N/A 4
32 ZPSE
N/A 4
S
0x000000
0x0000000
This location should not be written for
proper operation.
Register used in the digital integrator
algorithm. If the integrator is turned on, it
must be set at 0xFF8000. In practice, it is
transmitted as 0xFFF8000.
0x43B6
0x43B7
HPFDIS
Reserved
R/W
N/A 4
24
N/A 4
32 ZP
N/A 4
U
N/A 4
0x000000
0x000000
Disables/enables the HPF in the current
This memory location should be kept at
0x000000 for proper operation.
0x43B8
ISUMLVL
R/W
24
32 ZPSE
S
0x000000
Threshold used in comparison between
the sum of phase currents and the neutral
current ( ADE7868 and ADE7878 only).
Rev. H | Page 81 of 100
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