参数资料
| 型号： | IP-FFT |
| 厂商： | Altera |
| 文件页数： | 25/70页 |
| 文件大小： | 0K |
| 描述： | IP FFT/IFFT |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 快速傅里叶变换处理器 |
| 许可证： | 初始许可证 |
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2. Getting Started
Design Flows
The FFT MegaCore function supports the following design flows:
■
■
DSP Builder : Use this flow if you want to create a DSP Builder model that
includes a FFT MegaCore function variation.
MegaWizard? Plug-In Manager : Use this flow if you would like to create a FFT
MegaCore function variation that you can instantiate manually in your design.
This chapter describes how you can use a FFT MegaCore function in either of these
flows. The parameterization provides the same options in each flow and is described
After parameterizing and simulating a design in either of these flows, you can
compile the completed design in the Quartus II software.
DSP Builder Flow
Altera’s DSP Builder product shortens digital signal processing (DSP) design cycles
by helping you create the hardware representation of a DSP design in an
algorithm-friendly development environment.
DSP Builder integrates the algorithm development, simulation, and verification
capabilities of The MathWorks MATLAB ? and Simulink ? system-level design tools
with Altera Quartus ? II software and third-party synthesis and simulation tools. You
can combine existing Simulink blocks with Altera DSP Builder blocks and MegaCore
function variation blocks to verify system level specifications and perform simulation.
In DSP Builder, a Simulink symbol for the MegaCore function appears in the
MegaCore Functions library of the Altera DSP Builder Blockset in the Simulink library
browser.
You can use the FFT MegaCore function in the MATLAB/Simulink environment by
performing the following steps:
1. Create a new Simulink model.
2. Select the fft_ < version > block from the MegaCore Functions library in the
Simulink Library Browser, add it to your model, and give the block a unique
name.
3. Double-click on the fft_ < version > block in your model to display the parameter
editor and parameterize the MegaCore function variation. For an example of
setting parameters for the FFT MegaCore function, refer to “Parameterize the
4. Click Finish in the parameter editor to complete the parameterization and
generate your FFT MegaCore function variation. For information about the
5. Connect your FFT MegaCore function variation to the other blocks in your model.
November 2013
Altera Corporation
FFT MegaCore Function
User Guide
相关PDF资料 |
PDF描述 |
|---|---|
| IP-FIR | IP FIR COMPILER |
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPFH6N03LA G | 功能描述:MOSFET N-CH 25V 50A DPAK RoHS:是 类别:分离式半导体产品 >> FET - 单 系列:OptiMOS™ 标准包装:1,000 系列:MESH OVERLAY™ FET 型:MOSFET N 通道，金属氧化物 FET 特点:逻辑电平门 漏极至源极电压(Vdss):200V 电流 - 连续漏极(Id) @ 25° C:18A 开态Rds（最大）@ Id, Vgs @ 25° C:180 毫欧 @ 9A，10V Id 时的 Vgs(th)（最大）:4V @ 250µA 闸电荷(Qg) @ Vgs:72nC @ 10V 输入电容 (Ciss) @ Vds:1560pF @ 25V 功率 - 最大:40W 安装类型:通孔 封装/外壳:TO-220-3 整包 供应商设备封装:TO-220FP 包装:管件 |
| IPFH6N03LAG | 功能描述:MOSFET N-Channel MOSFET 20-200V RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| IP-FIR | 功能描述:开发软件 FIR Compiler MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPFLBPT2 | 制造商:Carlo Gavazzi 功能描述:IL 35MM MUSH P-P PL 22MM RED |
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