参数资料
| 型号： | IP-FFT |
| 厂商： | Altera |
| 文件页数： | 33/70页 |
| 文件大小： | 0K |
| 描述： | IP FFT/IFFT |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 快速傅里叶变换处理器 |
| 许可证： | 初始许可证 |
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Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
1
2–9
The complex multiplier implementation options Structure and Implement
Multipliers in are not available for the variable streaming architecture. The
complex multiplier implementation option DSP Resource Optimization is
available only in Stratix V devices.
If you turn on DSP Resource Optimization , and your variation has data precision
between 18 and 25 bits, inclusive, and twiddle precision less than or equal to 18
bits, the FFT MegaCore function configures the DSP blocks in complex 18 × 25
multiplication mode. If you turn on DSP Resource Optimization and your
variation does not meet these criteria, the FFT MegaCore function configures the
DSP blocks based on the criteria it uses when you do not turn on the option. The
FFT MegaCore function configures the Stratix V device according to the following
criteria when you turn off the option or it is not available:
■
■
■
If data precision and twiddle precision are both less than or equal to 27 bits,
configures 3/4 of a DSP block in complex 27 × 27 multiplication mode. This
configuration uses only three of the four DSP rows in a single DSP block.
If data precision is greater than 27 bits and twiddle precision is less than or
equal to 18 bits, configures one DSP block in sum of two 18 × 36 multiplication
mode. This configuration uses four DSP rows.
Otherwise, configures two DSP blocks in 36 × 36 multiplication mode. This
configuration uses eight DSP rows in two DSP blocks.
f For more information about the Stratix V DSP block modes, refer to the
Device Handbook .
8. Turn on Global Clock Enable , if you want to add a global clock enable to your
design.
9. Specify the memory options.
You can set memory use balance with the Twiddle ROM Distribution , turn on
Use M-RAM Blocks , and turn on Implement appropriate logic functions in
RAM . If your FFT variation targets an appropriate device family, the Use M144K
Blocks option replaces the Use M-RAM Blocks option.
1
The memory options are not available for the variable streaming
architecture. The memory options Twiddle ROM Distribution and Use
M-RAM Blocks are not available in the Cyclone series of device families
(the Cyclone, Cyclone II, Cyclone III, Cyclone III LS, and Cyclone IV device
families).
10. Click Finish when the implementation options are set.
November 2013
Altera Corporation
FFT MegaCore Function
User Guide
相关PDF资料 |
PDF描述 |
|---|---|
| IP-FIR | IP FIR COMPILER |
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPFH6N03LA G | 功能描述:MOSFET N-CH 25V 50A DPAK RoHS:是 类别:分离式半导体产品 >> FET - 单 系列:OptiMOS™ 标准包装:1,000 系列:MESH OVERLAY™ FET 型:MOSFET N 通道，金属氧化物 FET 特点:逻辑电平门 漏极至源极电压(Vdss):200V 电流 - 连续漏极(Id) @ 25° C:18A 开态Rds（最大）@ Id, Vgs @ 25° C:180 毫欧 @ 9A，10V Id 时的 Vgs(th)（最大）:4V @ 250µA 闸电荷(Qg) @ Vgs:72nC @ 10V 输入电容 (Ciss) @ Vds:1560pF @ 25V 功率 - 最大:40W 安装类型:通孔 封装/外壳:TO-220-3 整包 供应商设备封装:TO-220FP 包装:管件 |
| IPFH6N03LAG | 功能描述:MOSFET N-Channel MOSFET 20-200V RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| IP-FIR | 功能描述:开发软件 FIR Compiler MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPFLBPT2 | 制造商:Carlo Gavazzi 功能描述:IL 35MM MUSH P-P PL 22MM RED |
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