参数资料
| 型号： | IP-FFT |
| 厂商： | Altera |
| 文件页数： | 36/70页 |
| 文件大小： | 0K |
| 描述： | IP FFT/IFFT |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 快速傅里叶变换处理器 |
| 许可证： | 初始许可证 |
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2–12
Chapter 2: Getting Started
Simulate the Design
Table 2–1. Generated Files (Part 2 of 2)
Filename
(1)
&
(2)
Description
A MegaCore function variation file, which defines a VHDL or Verilog HDL top-level
< variation name >. vhd , or .v
< variation name > _1n1024cos.hex ,
< variation name > _2n1024cos.hex ,
< variation name > _3n1024cos.hex
< variation name > _1n1024sin.hex ,
< variation name > _2n1024sin.hex ,
< variation name > _3n1024sin.hex
< variation name > _model.m
< variation name > _tb.m
< variation name > _syn.v or
< variation name > _syn.vhd
< variation name > _tb.v or
< variation name > _tb.vhd
< variation name > _nativelink.tcl
description of the custom MegaCore function. Instantiate the entity defined by
this file inside of your design. Include this file when compiling your design in the
Quartus II software.
Intel hex-format ROM initialization files (not generated for variable streaming
FFT).
Intel hex-format ROM initialization files (not generated for variable streaming
FFT).
MATLAB m-file describing a MATLAB bit-accurate model.
MATLAB testbench.
A timing and resource netlist for use in some third-party synthesis tools.
Verilog HDL or VHDL testbench file.
Tcl Script that sets up NativeLink in the Quartus II software to natively simulate
< variation name > _twr1_opt.hex ,
< variation name > _twi1_opt.hex ,
< variation name > _twr2_opt.hex ,
< variation name > _twi2_opt.hex ,
< variation name > _twr3_opt.hex ,
Intel hex-format ROM initialization files (variable streaming FFT only).
< variation name > _twi3_opt.hex ,
< variation name > _twr4_opt.hex ,
< variation name > _twi4_opt.hex ,
(1) These files are variation dependent, some may be absent or their names may change.
(2) < variation name > is a prefix variation name supplied automatically by IP Toolbench.
2. After you review the generation report, click Exit to close IP Toolbench. Then click
Yes on the Quartus II IP Files prompt to add the . qip file describing your custom
MegaCore function to the current Quartus II project.
f Refer to the Quartus II Help for more information about the MegaWizard Plug-In
Manager.
You can now integrate your custom MegaCore function variation into your design
and simulate and compile.
Simulate the Design
This section describes the following simulation techniques:
FFT MegaCore Function
User Guide
■
■
November 2013 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-FIR | IP FIR COMPILER |
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPFH6N03LA G | 功能描述:MOSFET N-CH 25V 50A DPAK RoHS:是 类别:分离式半导体产品 >> FET - 单 系列:OptiMOS™ 标准包装:1,000 系列:MESH OVERLAY™ FET 型:MOSFET N 通道，金属氧化物 FET 特点:逻辑电平门 漏极至源极电压(Vdss):200V 电流 - 连续漏极(Id) @ 25° C:18A 开态Rds（最大）@ Id, Vgs @ 25° C:180 毫欧 @ 9A，10V Id 时的 Vgs(th)（最大）:4V @ 250µA 闸电荷(Qg) @ Vgs:72nC @ 10V 输入电容 (Ciss) @ Vds:1560pF @ 25V 功率 - 最大:40W 安装类型:通孔 封装/外壳:TO-220-3 整包 供应商设备封装:TO-220FP 包装:管件 |
| IPFH6N03LAG | 功能描述:MOSFET N-Channel MOSFET 20-200V RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| IP-FIR | 功能描述:开发软件 FIR Compiler MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPFLBPT2 | 制造商:Carlo Gavazzi 功能描述:IL 35MM MUSH P-P PL 22MM RED |
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