参数资料
| 型号： | IP-FFT |
| 厂商： | Altera |
| 文件页数： | 40/70页 |
| 文件大小： | 0K |
| 描述： | IP FFT/IFFT |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 快速傅里叶变换处理器 |
| 许可证： | 初始许可证 |
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2–16
Chapter 2: Getting Started
Compile the Design
Compile the Design
Use the Quartus II software to synthesize and place and route your design. Refer to
Quartus II Help for instructions on performing compilation.
Fixed Transform Architecture
To compile your fixed-transform architecture design, follow these steps:
1. If you are using the Quartus II software to synthesize your design, skip to step 2 . If
you are using a third-party synthesis tool to synthesize your design, follow these
steps:
a. Set a black box attribute for your FFT MegaCore function custom variation
before you synthesize the design. Refer to Quartus II Help for instructions on
setting black-box attributes per synthesis tool.
b. Run the synthesis tool to produce an EDIF Netlist File ( .edf ) or Verilog Quartus
Mapping (VQM) file ( .vqm ) for input to the Quartus II software.
c. Add the EDIF or VQM file to your Quartus II project.
1
The .qip file supersedes the files you had to add to the project explicitly in previous
versions of the Quartus II software. The .qip file contains the information about the
MegaCore function that the Quartus II software requires.
2. On the Processing menu, click Start Compilation .
Variable Streaming Architecture
To compile your variable streaming architecture design, follow these steps:
1. If you are using the Quartus II software to synthesize your design, skip to step 2 . If
you are using a third-party synthesis tool to synthesize your design, follow these
steps:
a. Set a black-box attribute for your FFT MegaCore function custom variation
before you synthesize the design. Refer to Quartus II Help for instructions on
setting black-box attributes per synthesis tool.
b. Run the synthesis tool to produce an EDIF Netlist File ( .edf ) or Verilog Quartus
Mapping (VQM) file ( .vqm ) for input to the Quartus II software.
c. Add the EDIF or VQM file to your Quartus II project.
2. On the Project menu, click Add/Remove Files in Project .
3. You can see a list of files in the project. If no files are listed, browse to the \lib
directory, then select and add all files with the prefix auk_dspip_r22sdf . Browse to
the < project > directory and select all files with prefix auk_dspip .
4. On the Processing menu, click Start Compilation .
Program a Device
After you have compiled your design, program your targeted Altera device, and
verify your design in hardware.
FFT MegaCore Function
User Guide
November 2013 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-FIR | IP FIR COMPILER |
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPFH6N03LA G | 功能描述:MOSFET N-CH 25V 50A DPAK RoHS:是 类别:分离式半导体产品 >> FET - 单 系列:OptiMOS™ 标准包装:1,000 系列:MESH OVERLAY™ FET 型:MOSFET N 通道，金属氧化物 FET 特点:逻辑电平门 漏极至源极电压(Vdss):200V 电流 - 连续漏极(Id) @ 25° C:18A 开态Rds（最大）@ Id, Vgs @ 25° C:180 毫欧 @ 9A，10V Id 时的 Vgs(th)（最大）:4V @ 250µA 闸电荷(Qg) @ Vgs:72nC @ 10V 输入电容 (Ciss) @ Vds:1560pF @ 25V 功率 - 最大:40W 安装类型:通孔 封装/外壳:TO-220-3 整包 供应商设备封装:TO-220FP 包装:管件 |
| IPFH6N03LAG | 功能描述:MOSFET N-Channel MOSFET 20-200V RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| IP-FIR | 功能描述:开发软件 FIR Compiler MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPFLBPT2 | 制造商:Carlo Gavazzi 功能描述:IL 35MM MUSH P-P PL 22MM RED |
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