参数资料
型号: IP-FFT
厂商: Altera
文件页数: 32/70页
文件大小: 0K
描述: IP FFT/IFFT
标准包装: 1
系列: *
类型: MegaCore
功能: 快速傅里叶变换处理器
许可证: 初始许可证
2–8
FFT MegaCore Function
User Guide
Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
6. Click the Implementation Options tab ( Figure 2–6 ).
Figure 2–6. Implementation Options Tab
7. Choose the complex multiplier implementation.
You can choose a Structure with three multipliers and five adders or four
multipliers and two adders. You can also choose to Implement Multipliers in DSP
blocks only, logic cells only or both DSP blocks and logic cells. If your FFT
variation targets a Stratix V device, you can turn on DSP Resource Optimization .
This option optimizes for area rather than speed by utilizing the new Stratix V
DSP block complex 18 × 25 and 27 × 27 multiplication modes. In the variable
streaming architecture using the floating point representation, the option utilizes
the DSP block complex 27 × 27 multiplication mode at the potential expense of
lower accuracy.
November 2013 Altera Corporation
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