参数资料
| 型号： | IP-FFT |
| 厂商： | Altera |
| 文件页数： | 61/70页 |
| 文件大小： | 0K |
| 描述： | IP FFT/IFFT |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 快速傅里叶变换处理器 |
| 许可证： | 初始许可证 |
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A. Block Floating Point Scaling
The FFT MegaCore function uses block-floating-point (BFP) arithmetic internally to
perform calculations. BFP architecture is a trade-off between fixed-point and full
floating-point architecture.
Unlike an FFT block that uses floating point arithmetic, a block-floating-point FFT
block does not provide an input for exponents. Internally, a complex value integer
pair is represented with a single scale factor that is typically shared among other
complex value integer pairs. After each stage of the FFT, the largest output value is
detected and the intermediate result is scaled to improve the precision. The exponent
records the number of left or right shifts used to perform the scaling. As a result, the
output magnitude relative to the input level is:
output*2 -exponent
For example, if exponent = –3, the input samples are shifted right by three bits, and
hence the magnitude of the output is output*2 3 .
Block Floating Point
After every pass through a radix-2 or radix-4 engine in the FFT core, the addition and
multiplication operations cause the data bits width to grow. In other words, the total
data bits width from the FFT operation grows proportionally to the number of passes.
The number of passes of the FFT/IFFT computation depends on the logarithm of the
number of points. Table A–1 on page A–2 shows the possible exponents for
corresponding bit growth.
A fixed-point architecture FFT needs a huge multiplier and memory block to
accommodate the large bit width growth to represent the high dynamic range.
Though floating-point is powerful in arithmetic operations, its power comes at the
cost of higher design complexity such as a floating-point multiplier and a floating-
point adder. BFP arithmetic combines the advantages of floating-point and fixed-
point arithmetic. BFP arithmetic offers a better signal-to-noise ratio (SNR) and
dynamic range than does floating-point and fixed-point arithmetic with the same
number of bits in the hardware implementation.
In a block-floating-point architecture FFT, the radix-2 or radix-4 computation of each
pass shares the same hardware, with the data being read from memory, passed
through the core engine, and written back to memory. Before entering the next pass,
each data sample is shifted right (an operation called "scaling") if there is a carry-out
bit from the addition and multiplication operations. The number of bits shifted is
based on the difference in bit growth between the data sample and the maximum data
sample detected in the previous stage. The maximum bit growth is recorded in the
exponent register. Each data sample now shares the same exponent value and data bit
width to go to the next core engine. The same core engine can be reused without
incurring the expense of a larger engine to accommodate the bit growth.
The output SNR depends on how many bits of right shift occur and at what stages of
the radix core computation they occur. In other words, the signal-to-noise ratio is data
dependent and you need to know the input signal to compute the SNR.
November 2013
Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-FIR | IP FIR COMPILER |
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPFH6N03LA G | 功能描述:MOSFET N-CH 25V 50A DPAK RoHS:是 类别:分离式半导体产品 >> FET - 单 系列:OptiMOS™ 标准包装:1,000 系列:MESH OVERLAY™ FET 型:MOSFET N 通道，金属氧化物 FET 特点:逻辑电平门 漏极至源极电压(Vdss):200V 电流 - 连续漏极(Id) @ 25° C:18A 开态Rds（最大）@ Id, Vgs @ 25° C:180 毫欧 @ 9A，10V Id 时的 Vgs(th)（最大）:4V @ 250µA 闸电荷(Qg) @ Vgs:72nC @ 10V 输入电容 (Ciss) @ Vds:1560pF @ 25V 功率 - 最大:40W 安装类型:通孔 封装/外壳:TO-220-3 整包 供应商设备封装:TO-220FP 包装:管件 |
| IPFH6N03LAG | 功能描述:MOSFET N-Channel MOSFET 20-200V RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| IP-FIR | 功能描述:开发软件 FIR Compiler MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPFLBPT2 | 制造商:Carlo Gavazzi 功能描述:IL 35MM MUSH P-P PL 22MM RED |
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