参数资料
| 型号： | IP-FFT |
| 厂商： | Altera |
| 文件页数： | 56/70页 |
| 文件大小： | 0K |
| 描述： | IP FFT/IFFT |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 快速傅里叶变换处理器 |
| 许可证： | 初始许可证 |
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3–14
Chapter 3: Functional Description
Parameters
Parameters
Table 3–3. Parameters (Part 1 of 3)
Parameter
Target Device Family
Value
< device family >
Description
Displays the target device family. The device family is normally
preselected by the project specified in the Quartus II software.
The generated HDL for your MegaCore function variation may
be incorrect if this value does not match the value specified in
the Quartus II project.
The device family must be the same as your Quartus II project
device family.
64, 128, 256, 512,
1024, 2048, 4096,
Transform Length
Data Precision
Twiddle Precision
FFT Engine Architecture
8192, 16384, 32768, or
65536. Variable
streaming also allows 8,
16, 32, 131072, and
262144.
8, 10, 12, 14, 16, 18,
20, 24, 28, 32
8, 10, 12, 14, 16, 18,
20, 24, 28, 32
Quad Output,
Single Output
The transform length. For variable streaming, this value is the
maximum FFT length.
The data precision. The values 28 and 32 are available for
variable streaming only.
The twiddle precision. The values 28 and 32 are available for
variable streaming only. Twiddle factor precision must be less
than or equal to data precision.
For both the Buffered Burst and Burst I/O data flow
architectures, you can choose between one, two, and four
quad-output FFT engines working in parallel. Alternatively, if
you have selected a single-output FFT engine architecture, you
may choose to implement one or two engines in parallel.
Multiple parallel engines reduce the FFT MegaCore function’s
transform time at the expense of device resources—which
Number of Parallel FFT Engines 1, 2, 4
allows you to select the desired area and throughput trade-off
point.
For more information about device resource and transform
time trade-offs, refer to “ “Parameters” on page 3–14 . Not
available for variable streaming or streaming architecture.
Streaming
I/O Data Flow
I/O Order
Data Representation
FFT MegaCore Function
User Guide
Variable Streaming
Buffered Burst
Burst
Bit Reverse Order, Digit
Reverse Order, Natural
Order, – N /2 to N /2
Fixed Point or Floating
Point
Choose the FFT architecture.
The input and output order for data entering and leaving the
FFT (variable streaming architecture only). The Digit Reverse
Order option replaces the Bit Reverse Order in variable
streaming floating point variations.
The internal data representation type (variable streaming
architecture only), either fixed point with natural bit-growth or
single precision floating point.
November 2013 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-FIR | IP FIR COMPILER |
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPFH6N03LA G | 功能描述:MOSFET N-CH 25V 50A DPAK RoHS:是 类别:分离式半导体产品 >> FET - 单 系列:OptiMOS™ 标准包装:1,000 系列:MESH OVERLAY™ FET 型:MOSFET N 通道，金属氧化物 FET 特点:逻辑电平门 漏极至源极电压(Vdss):200V 电流 - 连续漏极(Id) @ 25° C:18A 开态Rds（最大）@ Id, Vgs @ 25° C:180 毫欧 @ 9A，10V Id 时的 Vgs(th)（最大）:4V @ 250µA 闸电荷(Qg) @ Vgs:72nC @ 10V 输入电容 (Ciss) @ Vds:1560pF @ 25V 功率 - 最大:40W 安装类型:通孔 封装/外壳:TO-220-3 整包 供应商设备封装:TO-220FP 包装:管件 |
| IPFH6N03LAG | 功能描述:MOSFET N-Channel MOSFET 20-200V RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| IP-FIR | 功能描述:开发软件 FIR Compiler MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPFLBPT2 | 制造商:Carlo Gavazzi 功能描述:IL 35MM MUSH P-P PL 22MM RED |
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