参数资料
| 型号： | IP-FFT |
| 厂商： | Altera |
| 文件页数： | 39/70页 |
| 文件大小： | 0K |
| 描述： | IP FFT/IFFT |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 快速傅里叶变换处理器 |
| 许可证： | 初始许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页当前第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页
Chapter 2: Getting Started
2–15
Simulate the Design
function y = digit_reverse(x, n_bits)
if mod(n_bits,2)
z = dec2bin(x, n_bits);
for i=1:2:n_bits-1
p(:,i) = z(:,n_bits-i);
p(:,i+1) = z(:,n_bits-i+1);
end
p(:,n_bits) = z(:,1);
y=bin2dec(p);
else
y=digitrevorder(x,4);
end
Simulate with IP Functional Simulation Models
To simulate your design, use the IP functional simulation models generated by IP
Toolbench. The IP functional simulation model is the .vo or .vho file generated as
specified in “Set Up Simulation” on page 2–10 . Compile the .vo or . vho file in your
simulation environment to perform functional simulation of your custom variation of
the MegaCore function.
f For more information about IP functional simulation models, refer to the Simulating
Simulating in Third-Party Simulation Tools Using NativeLink
You can perform a simulation in a third-party simulation tool from within the
Quartus II software, using NativeLink.
f For more information about NativeLink, refer to the Simulating Altera Designs chapter
in volume 3 of the Quartus II Handbook .
You can use the Tcl script file < variation name > _nativelink.tcl to assign default
NativeLink testbench settings to the Quartus II project.
To set up simulation in the Quartus II software using NativeLink, follow these steps:
1. Create a custom variation but ensure you specify your variation name to match the
Quartus II project name.
2. Check that the absolute path to your third-party simulator executable is set. On the
Tools menu click Options and select EDA Tools Options .
3. On the Processing menu, point to Start and click Start Analysis & Elaboration .
4. On the Tools menu, click Tcl scripts . Select the < variation name > _nativelink.tcl Tcl
script and click Run . Check for a message confirming that the Tcl script was
successfully loaded.
5. On the Assignments menu, click Settings , expand EDA Tool Settings and select
Simulation . Select a simulator under Tool Name and in NativeLink Settings ,
select Test Benches .
6. On the Tools menu, point to EDA Simulation Tool and click Run EDA RTL
Simulation .
November 2013
Altera Corporation
FFT MegaCore Function
User Guide
相关PDF资料 |
PDF描述 |
|---|---|
| IP-FIR | IP FIR COMPILER |
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPFH6N03LA G | 功能描述:MOSFET N-CH 25V 50A DPAK RoHS:是 类别:分离式半导体产品 >> FET - 单 系列:OptiMOS™ 标准包装:1,000 系列:MESH OVERLAY™ FET 型:MOSFET N 通道，金属氧化物 FET 特点:逻辑电平门 漏极至源极电压(Vdss):200V 电流 - 连续漏极(Id) @ 25° C:18A 开态Rds（最大）@ Id, Vgs @ 25° C:180 毫欧 @ 9A，10V Id 时的 Vgs(th)（最大）:4V @ 250µA 闸电荷(Qg) @ Vgs:72nC @ 10V 输入电容 (Ciss) @ Vds:1560pF @ 25V 功率 - 最大:40W 安装类型:通孔 封装/外壳:TO-220-3 整包 供应商设备封装:TO-220FP 包装:管件 |
| IPFH6N03LAG | 功能描述:MOSFET N-Channel MOSFET 20-200V RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| IP-FIR | 功能描述:开发软件 FIR Compiler MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPFLBPT2 | 制造商:Carlo Gavazzi 功能描述:IL 35MM MUSH P-P PL 22MM RED |
发布紧急采购，3分钟左右您将得到回复。