
16.1.1.1 CLK Polarity
As shown in
Figure 16.12, the CKPOL bit in the UiC0 register (i = 0 to 4) determines the polarity of the serial
clock.
Figure 16.12
Serial Clock Polarity
16.1.1.2 LSB First or MSB First
As shown in
Figure 16.13, the UFORM bit in the UiC0 register (i = 0 to 4) determines a bit order
.
Figure 16.13
Bit Order (8-Bit Transfer Data Length)
CLKi
(1) When the CKPOL bit in the UiC0 register (i = 0 to 4) is set to 0 (transmit data output at the
falling edge and receive data input at the rising edge of the serial clock )
D0
D1
D3
D4
D5
D6
D7
D2
D0
D1
D3
D4
D5
D6
D7
D2
D0
D1
D3
D4
D5
D6
D7
D2
D0
D1
D3
D4
D5
D6
D7
D2
(2) When the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input
at the falling edge of the serial clock)
TXDi
RXDi
NOTES:
1. The above applies when the UFORM bit in the UiC0 register is set to 0 (LSB first) and the UiLCH bit in the
UiC1 register is set to 0 (not inverted).
2. The CLKi pin output level is "H" when no data is transferred.
3. The CLKi pin output level is "L" when no data is transferred.
"H"
"L"
"H"
"L"
"H"
"L"
CLKi
TXDi
RXDi
"H"
"L"
"H"
"L"
"H"
"L"
(note 2)
(note 3)
(1) When the UFORM bit in the UiC0 register (i = 0 to 4) is set to 0 (LSB first)
NOTE:
1. The above applies when the CKPOL bit in the UiC0 register is set to 0 (transmit data is output
at the falling edge of the serial clock and received data is input at the rising edge), and the
UiLCH bit in the UiC1 register is set to 0 (not inverted).
D0
D1
D3
D4
D5
D6
D7
D2
D0
D1
D3
D4
D5
D6
D7
D2
D0
D1
D3
D4
D5
D6
D7
D2
(2) When the UFORM bit is set to 1 (MSB first)
D0
D1
D3
D4
D5
D6
D7
D2
CLKi
TXDi
RXDi
"H"
"L"
"H"
"L"
"H"
"L"
CLKi
TXDi
RXDi
"H"
"L"
"H"
"L"
"H"
"L"