
16.1.5
Special Mode 3 (GCI Mode)
In GCI mode, the serial clock used in clock synchronous serial interface mode is synchronized with the external
clock.
settings.
Table 16.27
GCI Mode Specifications
NOTE:
1. If an overrun error occurs, the content of the UiRB register is undefined. The IR bit in the SiRIC register remains
unchanged as 0 (interrupt not requested).
Item
Specification
Transfer data format
Transfer data length: 8 bits long
Serial clock
Select the external clock
Set the CKDIR bit in the UiMR register (i = 0 to 4) to 1 (external clock)
Clock synchronization function
Trigger signal input to the CTSi pin
Transmit/receive start condition
After all of the following is met, a trigger signal must be input to the CTSi pin to
start transmit and receive operations:
Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
Set the RE bit in the UiC1 register to 1 (receive operation enabled)
The TI bit in the UiC1 register is 0 (data in the UiTB register)
Interrupt request generation timing While transmitting, one of the following conditions can be selected:
The UiIRS bit in the UiC1 register is set to 0 (no data in the UiTB register):
when data is transferred from the UiTB register to the UARTi transmit register
(transmit operation started)
The UiIRS bit is set to 1 (transmit operation completed):
when a data transmit operation from the UARTi transmit register is completed
While receiving,
when data is transferred from the UARTi receive register to the UiRB register
(receive operation completed)
Error detection
Overrun error occurs when the seventh bit of the next data is received before
reading the UiRB register