
Table 23.6
Interrupt Sources and Interrupt Registers (When INTSEL bit is Set to 1)
Figure 23.44
CAN2j Interrupt Block Diagram (When INTSEL Bit is Set to 1)
CAN2j interrupt source
CAN2j Interrupt
Intelligent I/O interrupt
Interrupt status bit
0: interrupt not
requested
1: interrupt requested
Interrupt mask bit
0: interrupt request
disabled
1: interrupt request
enabled
Intelligent I/O interrupt
request
0: interrupt not requested
1: interrupt requested
CAN2 message slot k
receive operation
completed
SISk bit in the
C2SISTR register
SIMk bit in the C2SIMKR
register
CAN20R bit in the IIO2IR
register
CAN2 message slot k
transmit operation
completed
CAN21R bit in the IIO3IR
register
CAN2 bus error detected
BEIS bit in the
C2EISTR register
BEIM bit in the C2EIMKR
register
CAN22R bit in the IIO6IR
register
CAN2 error-passive state
entered
EPIS bit in the
C2EISTR register
EPIM bit in the C2EIMKR
register
CAN2 bus-off state
entered
BOIS bit in the
C2EISTR register
BOIM bit in the
C2EIMKR register
CAN2 message slot 0
receive operation
completed
CAN2 message slot 0
transmit operation
completed
BEIS bit
BEIM bit
EPIS bit
EPIM bit
BOIS bit
BOIM bit
CAN2 bus error detected
CAN2 error-passive state
entered
CAN2 bus-off state
entered
SIS0 bit
SIM0 bit
CAN2 Interrupt
CAN2 message slot 31
receive operation
completed
CAN2 message slot 31
transmit operation
completed
SIS31 bit
SIM31 bit
CAN2 message slot 0
to 31 transmit operation
completed interrupt
request
CAN2 message slot 0
to 31 receive operation
completed interrupt
request
CAN2 error
interrupt request
INTSEL bit
CAN20R bit
Intelligent I/O
Interrupt
1
0
INTSEL bit
CAN21R bit
1
0
INTSEL bit
CAN22R bit
1
0