
10. Interrupts
10.5
Interrupts and Interrupt Vectors
There are four bytes in each vector. Set the start address of an interrupt routine in each interrupt vector table. When
an interrupt request is acknowledged, an interrupt routine is executed from the address set in the interrupt vector.
Figure 10.3
Interrupt Vector
10.5.1
Fixed Vector Tables
The fixed vector tables are allocated addresses FFFFDCh to FFFFFFh.
Table 10.1 lists the fixed vector tables.
Table 10.1
Fixed Vector Table
10.5.2
Relocatable Vector Tables
The relocatable vector tables occupy 256 bytes beginning from the start address set in the INTB register. Tables
10.2 and
10.3 list the relocatable vector tables.
Set an even address to the start address of the vector table set in the INTB register to increase interrupt sequence
execution rate.
Interrupt
Source
Vector Addresses
Address (L) to Address (H)
Remarks
Reference
Undefined
instruction
FFFFDCh to FFFFDFh
M32C/90 Series
Software Manual
Overflow
FFFFE0h to FFFFE3h
BRK instruction
FFFFE4h to FFFFE7h
If the content of address FFFFE7h is
FFh, a program is executed from the
address stored in the software interrupt
number 0 in the relocatable vector
table
Address match
FFFFE8h to FFFFEBh
FFFFECh to FFFFEFh
Reserved space
Watchdog timer
FFFFF0h to FFFFF3h
These addresses are used for the
watchdog timer interrupt and oscillation
stop detection interrupt
Reset,
Clock Generation Circuit,
Watchdog Timer
FFFFF4h to FFFFF7h
Reserved space
NMI
FFFFF8h to FFFFFBh
Reset
FFFFFCh to FFFFFFh
Reset
8 Middle-order bits of address
8 Low-order bits of address
00h
Vector address+0
LSB
MSB
Vector address+1
Vector address+2
Vector address+3
8 High-order bits of address