
Figure 14.12
TA0MR to TA4MR Registers in Event Counter Mode
b7
1
0
b6 b5 b4
b1
b2
b3
Symbol
TA0MR to TA4MR
Address
0356h, 0357h, 0358h, 0359h, 035Ah
After Reset
00h
b0
Function
(When not processing
two phase pulse signals)
Bit Symbol
Bit Name
RW
MR3
TCK1
Count polarity select bit(2)
RW
MR2
RW
MR1
TCK0
Timer Ai Mode Register (i = 0 to 4)(Event Counter Mode)
TMOD1
RW
Reserved bit
RW
(b2)
b1 b0
0 1: Event counter mode(1)
Operating mode select bits
TMOD0
RW
Set to 0
Increment/decrement
switching source select bit
NOTES:
1. Bits TAiTGH and TAiTGL in the ONSF or TRGSR register determine a count source in event counter mode.
2. The MR1 bit is enabled only when counting external signals.
3. Timer decrements a counter when an "L" signal is applied to the TAiOUT pin. The timer increments the counter value when an
"H" signal is applied to the TAiOUT pin.
4. The TCK1 bit is enabled only in the TA3MR register. The TCK1 bit in registers TA0MR to TA2MR and TA4MR are disabled.
5. For two-phase pulse signal processing, set the TAjP bit in the UDF register (j = 2 to 4) to 1 (two-phase pulse signal processing
function enabled). Also, set bits TAiTGH and TAiTGL in the TRGSR register to 00b (input to the TAjIN pin).
Function
(When processing
two phase pulse signals)
0: Falling edges of an
external signal counted
1: Rising edges of an
external signal counted
Set to 0
Set to 1
0: UDF registser setting
1: Signal applied to the
TAiOUT pin(3)
Count operation type
select bit
Two-phase pulse signal
processing operation
select bit(4,5)
0: Normal processing
operation
1: Multiply-by-4
processing operation
Set to 0 in event counter mode
0: Reload
1: Free running
Set to 0