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参数资料
| 型号： | NAND08GW3B2CZL1F |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 1G X 8 FLASH 3V PROM, 25000 ns, PBGA52 |
| 封装： | 12 X 17 MM, 1 MM PITCH, LEAD FREE, LGA-52 |
| 文件页数： | 14/72页 |
| 文件大小： | 1919K |
| 代理商： | NAND08GW3B2CZL1F |
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NAND04G-B2D, NAND08G-BxC
Command set
5
Command set
All bus write operations to the device are interpreted by the command interface. The
commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the command Latch Enable signal is High. Device operations are selected by writing specific
commands to the command register. The two-step command sequences for program and
erase operations are imposed to maximize data security.
Table 10 summarizes the commands.
Table 10.
Commands
Command(1)
1.
Commands in bold are referring to ONFI 1.0 specifications.
Bus write operations
Commands
accepted
during busy
1st cycle
2nd cycle
3rd cycle
4th cycle
Read
00h
30h
–
Random Data Output
05h
E0h
–
Cache Read (sequential)
31h
–
Enhanced Cache Read (random)
00h
31h
–
Exit Cache Read
3Fh
–
Yes(2)
2.
Only during cache read busy.
Page Program
(sequential input default)
80h
10h
–
Random Data Input
85h
–
Multiplane Page Program(3)
80h
11h
81h
10h
Multiplane Page Program
80h
11h
80h
10h
Copy Back Read
00h
35h
–
Copy Back Program
85h
10h
–
Multiplane Copy Back Program(3)
3.
Command maintained for backward compatibility.
85h
11h
81h
10h
Multiplane Copy Back Program
85h
11h
85h
10h
Block Erase
60h
D0h
–
Multiplane Block Erase(3)
60h
D0h
–
Multiplane Block Erase
60h
D1h
60h
D0h
Reset
FFh
–
Yes
Read Electronic Signature
90h
–
Read Status Register
70h
–
Yes
Read Status Enhanced
78h
–
Yes
Read Parameter Page
ECh
–
Read EDC Status Register
7Bh
–
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