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参数资料
| 型号： | NAND08GW3B2CZL1F |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 1G X 8 FLASH 3V PROM, 25000 ns, PBGA52 |
| 封装： | 12 X 17 MM, 1 MM PITCH, LEAD FREE, LGA-52 |
| 文件页数： | 26/72页 |
| 文件大小： | 1919K |
| 代理商： | NAND08GW3B2CZL1F |
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Device operations
NAND04G-B2D, NAND08G-BxC
Figure 17.
Multiplane copy back program
1.
This address scheme refers to x8 devices. Please, remember to use the appropriate scheme for x16 devices.
2.
Any command between 11h and 81h is prohibited except 70h and FFh.
6.7
Block erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
I/O
RB
Add. 5
cycles
ai13172c
00h
Read
code
Read
code
tBLBH1
(Read Busy time)
Busy
tBLBH1
(Read Busy time)
00h
Busy
35h
Read Status Register
10h
70h
SR0
Col. Add. 1, 2
Row Add. 1, 2, 3
Source address on 1st plane
35h
85h
Copy back
code
11h
81h
Copy back
code
tIPBSY
Busy
tBLBH2
(Program Busy time)
Busy
Col. Add. 1, 2
Row Add. 1, 2, 3
Source address on 2nd plane
Col. Add. 1, 2
Row Add. 1, 2, 3
Destination address
Col. Add. 1, 2
Row Add. 1, 2, 3
Destination address
A0-A11 = set to 'Low'
Add. 5
cycles
Add. 5
cycles
A12-A17 = set to 'Low'
A18 = set to 'Low'
A19-A28 = set to 'Low'
Add. 5
cycles
A0-A11 = set to 'Low'
A12-A17 = Valid
A18 = set to 'High'
A19-A28 = Valid
Source page
Target page
First plane
Main area
Spare area
Source page
Target page
Second plane
Main area
Spare area
(1)
(3)
(2)
(1): Read for copy back on first plane
(2): Read for copy back on second plane
(3): Two-plane copy back program
2
a) Traditional sequence.
W
CL
AL
R
60h R1A R2A R3A D1h
60h R1B R2B R3B
I/O 0-7
RB
Busy
tIPBSY
Busy
tBLBH2
(Program Busy time)
b) ONFI 1.0 sequence.
D0h
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