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参数资料
| 型号： | NAND08GW3B2CZL1F |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 1G X 8 FLASH 3V PROM, 25000 ns, PBGA52 |
| 封装： | 12 X 17 MM, 1 MM PITCH, LEAD FREE, LGA-52 |
| 文件页数： | 31/72页 |
| 文件大小： | 1919K |
| 代理商： | NAND08GW3B2CZL1F |
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NAND04G-B2D, NAND08G-BxC
Device operations
6.11.2
P/E/R controller and cache ready/busy bit (SR6)
Status register bit SR6 has two different functions depending on the current operation.
During cache operations, SR6 acts as a cache ready/busy bit, which indicates whether the
cache register is ready to accept new data. When SR6 is set to '0', the cache register is
busy, and when SR6 is set to '1', the cache register is ready to accept new data.
During all other operations, SR6 acts as a P/E/R controller bit, which indicates whether the
P/E/R controller is active or inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R
controller is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive
(device is ready).
6.11.3
P/E/R controller bit (SR5)
The Program/Erase/Read controller bit indicates whether the P/E/R controller is active or
inactive during cache operations. When the P/E/R controller bit is set to ‘0’, the P/E/R
controller is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive
(device is ready).
Note:
This bit is only valid for cache operations.
6.11.4
Error bit (SR0)
The error bit identifies if any errors have been detected by the P/E/R controller. The error bit
is set to ’1’ when a program or erase operation has failed to write the correct data to the
memory. If the error bit is set to ‘0’ the operation has completed successfully.
6.11.5
SR4, SR3, SR2 and SR1 are reserved
Table 14.
Status register bits
Bit
Name
Logic level
Definition
SR7
Write protection
'1'
Not protected
'0'
Protected
SR6
Program/Erase/Read controller
'1'
P/E/R controller inactive, device ready
'0'
P/E/R controller active, device busy
SR5
Program/Erase/Read controller(1)
'1'
P/E/R controller inactive, device ready
'0'
P/E/R controller active, device busy
SR4, SR3, SR2,
SR1
Reserved
‘don’t care’
SR0
Generic error
‘1’
Error – operation failed
‘0’
No error – operation successful
1.
Only valid for cache operations.
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