68
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
FPGA Conguration Modes (continued)
Note: M3 = GND for high-speed CCLK; M3 = VDD for low-frequency CCLK.
5-9739(F).a
Figure 40. Asynchronous Peripheral Conguration
Microprocessor Interface Mode
The built-in MPI in Series 4 FPGAs is designed for use in conguring the FPGA.
Figure 41 show the glueless inter-
face for FPGA conguration and readback from the PowerPC processor. When enabled by the mode pins, the MPI
handles all conguration/readback control and handshaking with the host processor. For single FPGA congura-
tion, the host sets the conguration control register MPI_PRGM to one then back to zero and, after reading that the
conguration write data acknowledge register is high, transfers data 8, 16, or 32 bits at a time to the FPGA’s D[#:0]
input pins. If conguring multiple FPGAs through daisy-chain operation is desired, the SYS_DAISY bit must be set
in the conguration control register of the MPI.
The conguration control register offers control bits to enable the interrupt on a bit stream error. The MPI status
register may be used in conjunction with, or in place of, the interrupt request option. The status register contains a
2-bit eld to indicate the bit stream error status. A ow chart of the MPI conguration process is shown in Figure 42. MICRO-
PRGM
ORCA
SERIES
FPGA
DOUT
CCLK
HDC
LDC
M2
M1
M0
VDD
TO DAISY-
CHAINED
DEVICES
PROCESSOR
D[7:0]
RDY/BUSY
INIT
DONE
ADDRESS
DECODE LOGIC
BUS
CONTROLLER
8
CS0
CS1
RD
WR