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80
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
TimingCharacteristics(continued)
PropagationDelay—Thetimebetweenthespecifiedreferencepoints.Thedelaysprovidedaretheworstcaseof
thetphhandtplldelaysfornoninvertingfunctions,tplhandtphlforinvertingfunctions,andtphzandtplzfor3-state
enable.
SetupTime—Theintervalimmediatelyprecedingthetransitionofaclockorlatchenablesignal,duringwhichthe
datamustbestabletoensureitisrecognizedastheintendedvalue.
HoldTime—Theintervalimmediatelyfollowingthetransitionofaclockorlatchenablesignal,duringwhichthe
datamustbeheldstabletoensureitisrecognizedastheintendedvalue.
3-StateEnable—Thetimefromwhena3-statecontrolsignalbecomesactiveandtheoutputpadreachesthe
high-impedancestate.
Table 39. PFU Timing Parameters
OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +85 C
Note:
AcompletelistingofPFUTimingParameterscanbedisplayedinORCAFoundry2001.Thisisasamplingofthekeytimingparameters.
Parameter
Symbol
Speed
Unit
–1
–2
–3
Min Max Min Max
Min
Max
Combinatorial Delays:
Four-input Variables to LUT out
Five-input Variables to LUT out
Six-input Variables to LUT out
F4_DEL
F5_DEL
F6_DEL
—
0.66
0.77
1.10
—
0.55
0.64
0.81
—
0.50
0.58
0.74
ns
Sequential Delays:
CLK Low Time
CLK High Time
Four-input Variables to Register CLK setup
Five-input Variables to Register CLK setup
Six-input Variables to Register CLK setup
Data In to Register CLK setup
Four-input Variables from Register CLK hold
Five-input Variables from Register CLK hold
Six-input Variables from Register CLK hold
Data In from Register CLK hold
Register CLK to Out
CLKL_MPW
CLKH_MPW
F4_SET
F5_SET
F6_SET
DIN_SET
F4_HLD
F5_HLD
F6_HLD
DIN-HLD
REG_DEL
0.36
0.40
0.28
0.38
0.71
0.00
0.10
0.00
0.25
1.03
—
0.35
0.38
0.23
0.28
0.63
0.00
0.16
0.10
0.24
0.92
—
0.32
0.35
0.21
0.25
0.57
0.00
0.15
0.09
0.22
0.84
—
ns
PFU CLK to Out (REG_DEL) Delay Adjustments
from Cycle Stealing:
One Delay Cell
Two Delay Cells
Three Delay Cells
CYCDEL1
CYCDEL2
CYCDEL3
0.89
1.64
2.43
—
0.70
1.29
1.98
—
0.64
1.18
1.80
—
ns