参数资料
型号: OR4E062BM680-DB
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: FPGA
英文描述: FPGA, 2024 CLBS, 515000 GATES, PBGA680
封装: PLASTIC, FBGA-680
文件页数: 98/151页
文件大小: 2680K
代理商: OR4E062BM680-DB
50
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Microprocessor Interface (continued)
Table 22. MPC 860 to ORCA MPI Interconnection
PowerPC
Signal
ORCA Pin
Name
MPI
I/O
Function
D[0:n]
I/O
8, 16, 32-bit data bus.
DP[0:m]
I/O
Selectable parity bus width from1, 2, and 4-bit.
A[14:31]
PPC_A[14:31]
I
32-bit MPI address bus.
TS
MPI_STRB
ITransfer start signal.
BURST
MPI_BURST
I
Active-low indicates burst transfer in-progress. High indicates current transfer
not a burst.
CS0
I
Active-low MPI select.
CS1
I
Active-high MPI select.
CLKOUT
MPI_CLK
I
PowerPC interface clock.
RD/WR
MPI_RW
I
Read (high)/write (low) signal.
TA
MPI_ACK
O
Active-low transfer acknowledge signal.
BDIP
MPI_BDIP
I
Active-low burst transfer in progress signal indicates that the second beat in
front of the current one is requested by the master. Negated before the burst
transfer ends to abort the burst data phase.
Any of
IRQ[7:0]
MPI_IRQ
O
Active-low interrupt request signal.
TEA
MPI_TEA
O
Active-low indicates MPI detects a bus error on the internal system bus for
current transaction.
RETRY
MPI_RTRY
O
Requests the MPC860/MPC8260 to relinquish the bus and retry the cycle.
TSZ[0:1]
MPI_TSZ[0:1]
I
Driven to indicate the data transfer size for the transaction (byte, half-word,
word).
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