![](http://datasheet.mmic.net.cn/160000/OR4E041BA352-DB_datasheet_9580481/OR4E041BA352-DB_72.png)
72
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
FPGA Conguration Modes (continued)
Slave Serial Mode
The slave serial mode is primarily used when multiple FPGAs are congured in a daisy-chain (see the Daisy-
Chaining section). It is also used on the FPGA evaluation board that interfaces to the download cable. A device in
the slave serial mode can be used as the lead device in a daisy-chain.
Figure 44 shows the connections for the
slave serial conguration mode.
The conguration data is provided into the FPGA’s DIN input synchronous with the conguration clock CCLK input.
After the FPGA has loaded its conguration data, it retransmits the incoming conguration data on DOUT at the ris-
ing edge of CCLK. CCLK is routed into all slave serial mode devices in parallel.
Multiple slave FPGAs can be loaded with identical congurations simultaneously. This is done by loading the con-
guration data into the DIN inputs in parallel.
5-4485(F).a
Figure 44. Slave Serial Conguration Schematic
Slave Parallel Mode
The slave parallel mode is essentially the same as the slave serial mode except that 8 bits of data are input on pins
D[7:0] for each CCLK cycle. Due to 8 bits of data being input per CCLK cycle, the DOUT pin does not contain a
valid bit stream for slave parallel mode. As a result, the lead device cannot be used in the slave parallel mode in a
daisy-chain conguration.
Figure 45 is a schematic of the connections for the slave parallel conguration mode. WR and CS0 are active-low
chip select signals, and CS1 is an active-high chip select signal. These chip selects allow the user to congure mul-
tiple FPGAs in slave parallel mode using an 8-bit data bus common to all of the FPGAs. These chip selects can
then be used to select the FPGAs to be congured with a given bit stream. The chip selects must be active for each
valid CCLK cycle until the device has been completely programmed. They can be inactive between cycles but must
meet the setup and hold times for each valid positive CCLK. D[7:0] of the FPGA can be connected to D[7:0] of the
microprocessor only if a standard prom le format is used. If a .bit or .rbt le is used from ORCA Foundry, then the
user must mirror the bytes in the .bit or .rbt le OR leave the .bit or .rbt le unchanged and connect D[7:0] of the
FPGA to D[0:7] of the microprocessor.
MICRO-
PROCESSOR
OR
DOWNLOAD
CABLE
M2
M1
M0
HDC
SERIES
FPGA
LDC
VDD
CCLK
PRGM
DOUT
TO DAISY-
CHAINED
DEVICES
DONE
DIN
INIT
ORCA
M3