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Lattice Semiconductor
91
Data Sheet
September, 2002
ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table56.PrimaryCLK(PCLK)Setup/HoldTimeusingon-chipPLLs(Pin-to-Pin)
OR4Exxx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C
< TJ
< +85 °C.
Notes:
1. Thepin-to-pintimingparametersinthistablewillmatchORCAFoundryiftheclockdelaymultiplierinthesetuppreferenceissetto0.95for
setuptimeand1.05forholdtime.
2. TimingusestheautomaticdelaycompensationmodeofthePLLs.ThefeedbacktothePLLisprovidedbytheglobalsystemclockrouting.
OtherdelayvaluesarepossiblebyusingthephasemodificationsmodeofthePLLinstead.
3. Thissetup/holdtimeisforafullyroutedclocktreethatusestheprimaryclocknetwork.ItincludesboththeLVTTL(3.3V)inputclockbuffer
delay,PLLblock,theclockroutingtothePIOCLKinput,thesetup/holdtimeofthePIOFF(withthedatainputdelaydisabled)andthe
LVTTL(3.3V)inputdatabuffertoPIOFFdelay.ThePCLKinputclockisconnectedatthesemi-dedicatedPLLinputpin.
4. NotethatthePIOcyclestealingdelayadjustmentsandthePLLcyclestealingdelayadjustmentsareeachattemptingtopullthesameclock
inbothdirections.Ifbotharebeingused,thenthedifferencebetweenthemwillprovidethebasisforPIOsetupandholdtimes.
5. FortimingimprovementsusingotherI/Obuffertypesfortheinputclockbufferorinputdatabuffer,see
Table45.Description
Device
Speed
Unit
-1
-2
-3
Min Max Min Max Min Max
Input to PCLK Setup Time, Input Data Delay Enabled
All
7.73
—
7.30
—
6.66
—
ns
Input to PCLK Setup Time, No Input Data Delay
All
0.00
—
0.00
—
0.00
—
ns
Input to PCLK Hold Time, Input Data Delay Enabled
All
0.00
—
0.00
—
0.00
—
ns
Input to PCLK Hold Time, No Input Data Delay
All
1.82
—
1.73
—
1.57
—
ns
Input Delay Adjustments from PIO Cycle Stealing
(typically used to reduce setup time by the min value
shown):
One Delay Cell
Two Delay Cells
Three Delay Cells
ICYCDEL1
ICYCDEL2
ICYCDEL3
—
0.89
1.64
2.43
—
0.70
1.29
1.98
—
0.64
1.18
1.80
ns
PLL Delay Adjustments from Cycle Stealing (used to
reduce hold by the min delay value shown):
One Delay Cell
Two Delay Cells
Three Delay Cells
PLLCDEL1
PLLCDEL2
PLLCDEL3
—
0.89
1.64
2.43
—
0.70
1.29
1.98
—
0.64
1.18
1.80
ns