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| 型号： | OR4E062BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 2024 CLBS, 515000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 94/151页 |
| 文件大小： | 2680K |
| 代理商： | OR4E062BM680-DB |
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Data Sheet
September, 2002
Lattice Semiconductor
47
ORCA Series 4 FPGAs
Special Function Blocks (continued)
5-5971(F)
Figure 30. Instruction Register Scan Timing Diagram
TCK
TMS
TDI
RUN-TEST/IDLE
EXIT1-IR
EXIT2-IR
UPDATE-IR
SELECT-DR-SCAN
CAPTURE-IR
SELECT-IR-SCAN
TEST-LOGIC-RESET
SHIFT-IR
PAUSE-IR
SHIFT-IR
EXIT1-IR
Single Function Blocks
Most of the special function blocks perform a specic
dedicated function. These functions are data/congura-
tion readback control, global 3-state control (TS_ALL),
internal oscillator generation, GSRN, and start-up
logic.
Readback Logic
The readback logic can be enabled via a bit stream
option or by instantiation of a library readback compo-
nent.
Readback is used to read back the conguration data
and, optionally, the state of the PFU outputs. A read-
back operation can be done while the FPGA is in nor-
mal system operation. The readback operation cannot
be daisy-chained. To use readback, the user selects
options in the bit stream generator in the ORCA
Foundry development system.
Table 21 provides readback options selected in the bit
stream generator tool. The table provides the number
of times that the conguration data can be read back.
This is intended primarily to give the user control over
the security of the FPGA’s conguration program. The
user can prohibit readback (0), allow a single readback
(1), or allow unrestricted readback (U).
Table 21. Readback Options
Readback can be performed via the Series 4 MPI or by
using dedicated FPGA readback controls. If the MPI is
enabled, readback via the dedicated FPGA readback
logic is disabled. Readback using the MPI is discussed
in the MPI section.
The pins used for dedicated readback are readback
data (RD_DATA), read conguration (RD_CFG), and
conguration clock (CCLK). A readback operation is
initiated by a high-to-low transition on RD_CFG. The
RD_CFG
input must remain low during the readback
operation. The readback operation can be restarted at
frame 0 by driving the RD_CFG pin high, applying at
least two rising edges of CCLK, and then driving
RD_CFG
low again. One bit of data is shifted out on
RD_DATA at the rising edge of CCLK. The rst start bit
of the readback frame is transmitted out several cycles
after the rst rising edge of CCLK after RD_CFG is input
low (see the readback timing characteristics table in the
timing characteristics section). To be certain of the start
of the readback frame, the data can be monitored for
the 01 frame start bit pair.
Option
Function
0
ProhibitReadback
1
AllowOneReadbackOnly
U
AllowUnrestrictedNumberofReadbacks
相关PDF资料 |
PDF描述 |
|---|---|
| OR4E063BA352-DB | FPGA, 2024 CLBS, 515000 GATES, PBGA352 |
| OR4E063BM680-DB | FPGA, 2024 CLBS, 515000 GATES, PBGA680 |
| ORT4622-8BC432I | FPGA, PBGA432 |
| ORT4622-8BM680I | FPGA, PBGA680 |
| ORT4622-8BC432I | FPGA, PBGA432 |
相关代理商/技术参数 |
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| OR4E10 | 制造商:AGERE 制造商全称:AGERE 功能描述:Field-Programmable Gate Arrays |
| OR4E14 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Gate Arrays |
| OR4E2 | 制造商:AGERE 制造商全称:AGERE 功能描述:Field-Programmable Gate Arrays |
| OR4E2-1BA256 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| OR4E2-1BA352 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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