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Lattice Semiconductor
105
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Pin Information (continued)
Package Compatibility
Table 68 provides the number of user I/Os available for the ORCA Series 4 FPGAs for each available package.
Each package has six dedicated conguration pins.
Table69thru
Table71providethepackagepinandpinfunctionfortheSeries4FPGAsandpackages.Thebond
padnameisidentifiedinthePIOnomeclatureusedintheORCAFoundrydesigneditor.TheBankcolumnprovides
informationastowhichoutputvoltagelevelbankthegivenpinisin.TheGroupcolumnprovidesinformationasto
thegroupofpinsthegivenpinisin.ThisisusedtoshowwhichVREFpinisusedtoprovidethereferencevoltage
forsingle-endedlimited-swingI/Os.Ifnoneofthesebuffertypes(suchasSSTL,GTL,HSTL)areusedinagiven
group,thentheVREFpinisavailableasanI/Opin.
WhenthenumberofFPGAbondpadsexceedsthenumberofpackagepins,bondpadsareunused.Whenthe
numberofpackagepinsexceedsthenumberofbondpads,packagepinsareleftunconnected(noconnects).
Whenapackagepinistobeleftasanoconnectforaspecificdie,itisindicatedasanoteinthedevicecolumnfor
theFPGA.Thetablesprovidenoinformationonunusedpads.
Inordertoallowpin-for-pincompatibleboardlayoutsthatcanaccommodatebothdevices,somekeycompatibility
issuesincludethefollowing.:
■
SharedControlSignalsonI/ORegisters.TheORCASeries4architecturesharesclockandcontrolsignals
betweentwoadjacentI/Opads.IfI/Oregistersareused,incompatibilitiesmayarisebetweendeviceswhendif-
ferentclockorcontrolsignalsareneededonadjacentpackagepins.Thisisbecauseonedevicemayallowinde-
pendentclockorcontrolsignalsontheseadjacentpins,whiletheothermayforcethemtobethesame.There
aretwowaystoavoidthisissue.
—Alwayskeepanopenbondedpin(non-bondedpinsdonotcount)betweenpinsthatrequiredifferentclockor
controlsignals.NotethatthisopenpincanbeusedtoconnectsignalsthatdonotrequiretheuseofI/Oregis-
terstomeettiming.
—Placeandroutethedesigninalltargetdevicestoverifytheyproducevaliddesigns.Notethatthismethod
guaranteesthecurrentdesign,butdoesnotnecessarilyguardagainstissuesthatcanoccurwhendesign
changesaremadethataffectI/Oregisters.
—2X/4XI/OShiftRegisters.If2XI/Oshiftregistersor4XI/Oshiftregistersareusedinthedesign,thismay
causeincompatibilitiesbetweenthedevicesbecauseonlytheAandCI/OsinaPICsupport2XI/Oshiftregis-
tersandonlyAI/Ossupports4XI/Oshiftregistermode.AandCI/Osareshowninthefollowingpinouttables
undertheI/OpadcolumnsasthoseendinginAorC.
■
Edge Clock Input Pins. The input buffers for fast edge clocks are only available at the C I/O pad. The C I/Os are
shown in the following pinout tables under the I/O pad columns as those ending in C.
■
680 PBGAM Differential I/O Pairs. Note that the OR4E02 device in the 680 PBGAM package has two less dif-
ferential I/O pairs available than the OR4E04 or OR4E06, even though the total number of user I/Os are the same
for all three devices.