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参数资料
| 型号： | RJ80530LZ001512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | MICRO, FCPGA-478 |
| 文件页数： | 30/96页 |
| 文件大小： | 2018K |
| 代理商： | RJ80530LZ001512 |
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Electrical Specifications
R
36
Mobile Intel
Pentium III Processor-M Datasheet
Table 18. CLKREF, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
VIL15
Input Low Voltage, 1.5 V CMOS
–0.15
VCMOSREFmin
– 300 mV
V
VIL18
Input Low Voltage, 1.8 V CMOS
–0.36
0.36
V
Notes 1, 2
VIH15
Input High Voltage, 1.5 V CMOS
VCMOSREFmax +
250 mV
2.0
V
Note 11
VIH15PICD
Input High Voltage, 1.5 V PICD[1:0]
VCMOSREFmax +
200 mV
2.0
V
Note 12
VIH18
Input High Voltage, 1.8 V CMOS
1.44
2.0
V
Notes 1, 2
VOH15
Output High Voltage, 1.5 V CMOS
N/A
1.615
V
All outputs are Open-drain
VOH33
Output High Voltage, 3.3 V signals
2.0
3.465
V
3.3V + 5%
VOL33
Output Low Voltage, 3.3 V signals
0.8
V
VOL
Output Low Voltage
0.3
V
Note 9
VCMOSREF
CMOSREF Voltage
0.90
1.10
V
Note 4
VCLKREF
CLKREF Voltage
1.187
1.312
V
Note 10
VILVTTPWR
Input Low Voltage, VTTPWRGD
0.4
V
Note 7
VIHVTTPWR Input High Voltage, VTTPWRGD
1.0
V
Note 7
VILGHI
Input Low Voltage, GHI#
0.2
V
Note 8
VIHGHI
Input High Voltage, GHI#
1.0
V
Note 8
RON
30
Note 3
IOL
Output Low Current
10
mA
Note 6
IL
Leakage Current for Inputs, Outputs
and I/Os
±100
A
Note 5
NOTES:
1.
Parameter applies to the PWRGOOD signal only.
2.
VILx,min and VIHx,max only apply when BCLK, BCLK# and PICCLK are stopped. PICCLK should be stopped in the
low state. See Table 30 and Table 31 for DC levels when BCLK and BCLK# are stopped.
3.
Measured at 9 mA.
4.
VCMOSREF should be created from a stable 1.5-V supply using a voltage divider. It must track the voltage supply
to maintain noise immunity. The same 1.5-V supply should be used to power the chipset CMOS I/O buffers that
drive these signals.
5.
(0
≤ VIN/OUT ≤ VIHx,max).
6.
Specified as the minimum amount of current that the output buffer must be able to sink. However, VOL,max cannot
be guaranteed if this specification is exceeded.
7.
Parameter applies to VTTPWRGD signal only.
8.
Parameter applies to GHI# signal only.
9.
Applies to non-AGTL signals except BCLK, PWRGOOD, PICCLK, BSEL[1:0], VID[4:0].
10. ±5% DC tolerance. CLKREF must be generated from the same 2.5-V supply used to generate the BCLK signal.
AC Tolerance must be less than –40 dB at 1 MHz. The CLKREF DC spec only applies to platforms supporting
single-ended clocking.
11. Applies to all TAP and CMOS signals (not to APIC signals).
12. Applies to PICD[1:0].
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