Introduction
R
Mobile Intel
Pentium III Processor-M Datasheet
9
Mobile Intel Pentium Processor-M
Product Features
Supports Enhanced Intel SpeedStep
technology with the following
Processor core/bus speeds:
1.333 GHz/133 MHz (Maximum
Performance Mode) and 800/133 MHz
(Battery Optimized Mode)
1.266 GHz/133 MHz (Maximum
Performance Mode) and 800/133 MHz
(Battery Optimized Mode)
1.200 GHz/133 MHz (Maximum
Performance Mode) and 800/133 MHz
(Battery Optimized Mode)
1.133 GHz/133 MHz (Maximum
Performance Mode) and 733/133 MHz
(Battery Optimized Mode)
1.066 GHz/133 MHz (Maximum
Performance Mode) and 733/133 MHz
(Battery Optimized Mode)
1.000 GHz/133 MHz (Maximum
Performance Mode) and 733/133 MHz
(Battery Optimized Mode)
Low Voltage processors support Enhanced
Intel SpeedStep technology with the following
Processor core/bus speeds:
1.00GHz/133 MHz (Maximum
Performance Mode) and 533/133 MHz
(Battery Optimized Mode)
933/133 MHz (Maximum Performance
Mode) and 533/133 MHz (Battery
Optimized Mode)
866/133 MHz (Maximum Performance
Mode) and 533/133 MHz (Battery
Optimized Mode)
800/133 MHz (Maximum Performance
Mode) and 533/133 MHz (Battery
Optimized Mode)
850/100 MHz (Maximum Performance
Mode) and 500/100 MHz (Battery
Optimized Mode)
800A/100 MHz (Maximum Performance
Mode) and 500/100 MHz (Battery
Optimized Mode)
Ultra Low Voltage processors support
Enhanced Intel SpeedStep technology
with the following Processor core/bus
speeds:
933/133 MHz (Maximum
Performance Mode) and 400/133
MHz (Battery Optimized Mode)
900/100 MHz (Maximum
Performance Mode) and 400/100
MHz (Battery Optimized Mode)
866/133 MHz (Maximum
Performance Mode) and 400/133
MHz (Battery Optimized Mode)
850/133 MHz (Maximum
Performance Mode) and 400/133
MHz (Battery Optimized Mode)
800/133 MHz (Maximum
Performance Mode) and 400/133
MHz (Battery Optimized Mode)
800/100 MHz (Maximum
Performance Mode) and 400/100
MHz (Battery Optimized Mode)
Feature Highlights
Supports the Intel Architecture with
Dynamic Execution
On-die primary 16-Kbyte instruction cache
and 16-Kbyte write-back data cache
On-die second level cache (512-Kbyte)
with Advanced Transfer Cache
Architecture
Data Prefetch Logic
Integrated AGTL termination
Integrated math co-processor
Micro-FCPGA and Micro-FCBGA
packaging technologies
Supports thin form factor notebook
designs
Exposed die enables more efficient
heat dissipation
Fully compatible with previous Intel
microprocessors
Binary compatible with all
applications
Support for MMX technology
Support for Streaming SIMD
Extensions