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参数资料
| 型号： | RJ80530LZ001512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | MICRO, FCPGA-478 |
| 文件页数： | 9/96页 |
| 文件大小： | 2018K |
| 代理商： | RJ80530LZ001512 |
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Mobile Intel Pentium III Processor-M Features
R
Mobile Intel
Pentium III Processor-M Datasheet
17
Figure 1. Clock Control States
Quick Start
Normal
HS=false
Deep Sleep 2
HALT/Grant
Snoop
Auto Halt
HS=true
Deeper
Sleep
STPCLK#1
BCLK stopped
or DPSLP#
snoop
occurs
BCLK on
and !DPSLP#
(!STPCLK# and !HS)
or RESET#
snoop
serviced
HLT
instruction 1
snoop
serviced
snoop
occurs
core
voltage
raised
core
voltage
reduced
STPCLK#1
!STPCLK#
and HS
halt
break
V0001-02
NOTES:
1. State transition does not occur until the Stop Grant or Auto Halt acknowledge bus cycle completes
Halt break – A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
HLT – HLT instruction executed
HS – Processor Halt State
2. Restrictions apply to the use of both methods of entering Deep Sleep. See Deep Sleep state description for details.
2.2.4
Quick Start State
The processor is required to be configured for the Quick Start state by strapping the A15# signal low.
More details are provided in Section 7.1. In the Quick Start state the processor is only capable of acting
on snoop transactions generated by the system bus priority device. Because of its snooping behavior,
Quick Start can only be used in a uniprocessor (UP) configuration.
A transition to the Deep Sleep state can be made by stopping the clock input to the processor or
asserting the DPSLP# signal. A transition back to the Normal state (from the Quick Start state) is made
only if the STPCLK# signal is deasserted.
While in the Quick Start state the processor is limited in its ability to respond to input. It is incapable
of latching any interrupts, servicing snoop transactions from symmetric bus masters or responding to
FLUSH# or BINIT# assertions. While the processor is in the Quick Start state, it will not respond
properly to any input signal other than STPCLK#, RESET#, or BPRI#. If any other input signal
changes, then the behavior of the processor will be unpredictable. No serial interrupt messages may
begin or be in progress while the processor is in the Quick Start state.
RESET# assertion will cause the processor to immediately initialize itself, but the processor will stay
in the Quick Start state after initialization until STPCLK# is deasserted.
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