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| 型号： | RJ80530LZ001512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | MICRO, FCPGA-478 |
| 文件页数： | 76/96页 |
| 文件大小： | 2018K |
| 代理商： | RJ80530LZ001512 |
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Processor Initialization and Configuration
R
78
Mobile Intel
Pentium III Processor-M Datasheet
7.
Processor Initialization and
Configuration
7.1
Description
The Mobile Intel Pentium III Processor-M has some configuration options that are determined by
hardware and some that are determined by software. The processor samples its hardware configuration
at reset on the active-to-inactive transition of RESET#. The P6 Family of Processors Developer’s
Manual describes these configuration options. Some of the configuration options for the Mobile Intel
Pentium III Processor-M are described in the remainder of this section.
7.1.1
Quick Start Enable
Quick Start enabling is mandatory on the Mobile Intel Pentium III Processor-M by strapping A15# low.
When the STPCLK# signal is asserted it will enter the Quick Start state when A15# is sampled active
on the RESET# signal’s active-to-inactive transition. The Quick Start state supports snoops from the
bus priority device but it does not support symmetric master snoops nor is the latching of interrupts
supported. A “1” in bit position 5 of the Power-on Configuration register indicates that the Quick Start
state has been enabled.
7.1.2
System Bus Frequency
The current generation Mobile Intel Pentium III Processor-M will only function with a system bus
frequency of 133 MHz. The Low Voltage Mobile Intel Pentium III Processor-M will support both 100-
MHz and 133-MHz bus frequencies. The Ultra Low Voltage Mobile Intel Pentium III Processor-M
will support both 100-MHz and 133-MHz bus frequencies (see product features section for specific
supported frequencies). Bit positions 18 to 19 of the Power-on Configuration register indicates at
which speed a processor will run.
7.1.3
APIC Enable
The processor APIC must be hardware enabled by pulling the PICD[1:0] signals separately up to 1.5 V
and supplying an active PICCLK to the processor. Software can be used to disable the APIC if it is not
being used, after PICD[1:0] are sampled high when RESET# is deasserted and the processor has
started executing instructions.
7.2
Clock Frequencies and Ratios
The Mobile Intel Pentium III Processor-M uses a clock design in which the bus clock is multiplied by a
ratio to produce the processor’s internal (or “core”) clock. The ratio used is programmed into the
processor during manufacturing. The bus ratio programmed into the processor is visible in bit positions
22 to 25 and 27 of the Power-on Configuration register. Table 22 shows the 5-bit codes in the Power-
on Configuration register and their corresponding bus ratios.
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