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参数资料
| 型号： | RJ80530LZ001512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | MICRO, FCPGA-478 |
| 文件页数： | 35/96页 |
| 文件大小： | 2018K |
| 代理商： | RJ80530LZ001512 |
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Electrical Specifications
R
40
Mobile Intel
Pentium III Processor-M Datasheet
Table 23. AGTL Signal Groups AC Specifications
1
RTT = 56 internally terminated to VCCT; VREF =
2/3VCCT; load = 50 ohms
Symbol
Parameter
Min
Max
Unit
Figure
Notes
T7
AGTL Output Valid Delay
0.40
3.25
ns
9
T8
AGTL Input Setup Time
0.95
1.30
ns
10
Notes 2, 3, 6
Note 7
T9
AGTL Input Hold Time
1
ns
10
Note 4
T10
RESET# Pulse Width
1
ms
11,12
Note 5
NOTES:
1.
All AC timings for AGTL signals are referenced to the crossing point of the BCLK rising edge and the BCLK#
falling edge for Differential Clocking and to the BCLK rising edge at 1.25 V for Single Ended Clocking. All AGTL
signals are referenced at VREF. Unless other specified, all timings apply to both 100 and 133 MHz bus
frequencies.
2.
RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
3.
Specification is for a minimum 0.40-V swing from Vref-200 mV to Vref+200 mV.
4.
Specification is for a maximum 0.8-V swing from Vcct-0.8 V to Vcct.
5.
After VCC, VCCT, and BCLK, BCLK# become stable and PWRGOOD is asserted.
6.
Applies to processors supporting 133-MHz bus clock frequency except Ultra Low Voltage processors.
7.
Applies to processors supporting 100-MHz bus clock frequency and Ultra Low Voltage processors supporting
133-MHz bus clock frequency.
Table 24. CMOS and Open-drain Signal Groups AC Specifications
1, 2
Symbol
Parameter
Min Max
Unit
Figure
Notes
T14
1.5V Input Pulse Width, except PWRGOOD and
LINT[1:0]
2
BCLKs 11
Active and inactive
states
T14B
LINT[1:0] Input Pulse Width
6
BCLKs 11
Note 3
T15
PWRGOOD Inactive Pulse Width
2
s
12
Note 4, 5
NOTES:
1.
All AC timings for CMOS and Open-drain signals are referenced to the crossing point of the BCLK rising edge
and BCLK# falling edge for Differential Clocking and to the rising edge of BCLK at 1.25V for Single Ended
Clocking. All CMOS and Open-drain signals are referenced at 1.0 V.
2.
Minimum output pulse width on CMOS outputs is 2 BCLKs.
3.
This specification only applies when the APIC is enabled and the LINT1 or LINT0 signal is configured as an
edge triggered interrupt with fixed delivery, otherwise specification T14 applies.
4.
When driven inactive, or after VCC, VCCT and BCLK, BCLK# become stable. PWRGOOD must remain below
VIL18,MAX until all the voltage planes meet the voltage tolerance specifications in Table 9 through Table 15 and
BCLK, BCLK# have met the BCLK, BCLK# AC specifications in Table 30 and Table 31 for at least 2
s.
PWRGOOD must rise error-free and monotonically to 1.8 V.
5.
If the BCLK Settling Time specification (T60) can be guaranteed at power-on reset then the PWRGOOD
Inactive Pulse Width specification (T15) is waived and BCLK may start after PWRGOOD is asserted.
PWRGOOD must still remain below VIL18,max until all the voltage planes meet the voltage tolerance
specifications.
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