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参数资料
| 型号： | RJ80530LZ001512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | MICRO, FCPGA-478 |
| 文件页数： | 49/96页 |
| 文件大小： | 2018K |
| 代理商： | RJ80530LZ001512 |
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System Signal Simulations
R
Mobile Intel
Pentium III Processor-M Datasheet
53
4.
System Signal Simulations
Systems must be simulated using IBIS models to determine if they are compliant with this
specification. All references to BCLK signal quality also apply to BCLK# for Differential Clocking.
4.1
System Bus Clock (BCLK) and PICCLK DC
Specifications and AC Signal Quality
Specifications
Table 30. BCLK (Differential) DC Specifications and AC Signal Quality Specifications
Symbol
Parameter
Min
Max
Unit Figure
Notes
V1
VIL,BCLK
-0.2
0.35
V
7
Note 1
V2
VIH,BCLK
0.92
1.45
V
7
Note 1
V3
VIN Absolute Voltage Range
-0.2
1.45
V
7
Undershoot/Overshoot, Note 2
V4
BCLK Rising Edge Ringback
0.35
V
8
Note 3
V5
BCLK Falling Edge Ringback
-0.35
V
8
Note 3
VBCLK_DPSLP
BCLK Voltage in Deep Sleep
State
0.4
1.45
V
Note 4
VBCLK#_DPSLP BCLK# Voltage in Deep Sleep
State
0
VBCLK_DPSLP
- 0.2V
V
Note 4
NOTES:
1.
The clock must rise/fall monotonically between VIL,BCLK and VIH,BCLK .
2.
These specifications apply only when BCLK, BCLK# are running.
3.
The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) voltage the
differential waveform can go to after passing the VIH_DIFF (rising) or VIL_DIFF (falling) levels. VIL_DIFF (max)
= -0.57 V, VIH_DIFF (min) = 0.57 V.
4.
Applies when BCLK and BCLK# are stopped in Deep Sleep State.
Table 31. BCLK (Single Ended) DC Specifications and AC Signal Quality Specifications
Symbol
Parameter
Min
Max
Unit
Figure
Notes
V1
VIL,BCLK
0.3
V
20
Note 1
V2
VIH,BCLK
2.2
V
20
Note 1
V3
VIN Absolute Voltage Range
-0.5
3.1
V
20
Undershoot/Overshoot, Note 2
V4
BCLK Rising Edge Ringback
2.0
V
20
Absolute Value, Note 3
V5
BCLK Falling Edge Ringback
0.5
V
20
Absolute Value, Note 3
NOTES:
1.
The clock must rise/fall monotonically between VIL,BCLK and VIH,BCLK . BCLK must be stopped in the low state.
2.
These specifications apply only when BCLK is running. BCLK may not be above VIH,BCLK,max or below VIL,BCLK,min
for more than 50% of the clock cycle.
3.
The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can go to after passing the VIH,BCLK (rising) or VIL,BCLK (falling) voltage limits.
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