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参数资料
| 型号： | RJ80530LZ001512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | MICRO, FCPGA-478 |
| 文件页数： | 31/96页 |
| 文件大小： | 2018K |
| 代理商： | RJ80530LZ001512 |
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Electrical Specifications
R
Mobile Intel
Pentium III Processor-M Datasheet
37
3.7
AC Specifications
3.7.1
System Bus, Clock, APIC, TAP, CMOS, and Open-
drain AC Specifications
All system bus AC specifications for the AGTL signal group are relative to the crossing point of the
rising edge of the BCLK input and falling edge of the BCLK# input. All AGTL timings are referenced
to VREF for both “0” and “1” logic levels unless otherwise specified. All APIC, TAP, CMOS, and
Open-drain signals except PWRGOOD are referenced to 1.0 V. All minimum and maximum
specifications are at points within the power supply ranges shown in Table 9 through Table 15 and
junction temperatures (Tj) in the range 0
°C to 100°C. Tj must be less than or equal to 100°C for all
functional processor states.
Table 19. System Bus Clock AC Specifications (Differential)
1
Symbol
Parameter
Min
Typ
Max Unit
Figure
Notes
System Bus Frequency
133
MH
z
T1
BCLK Period - average
7.5
7.7
ns
8
Note 2
T1abs
BCLK Period – Instantaneous minimum
7.3
ns
8
Note 2
T2
BCLK Cycle to Cycle Jitter
200
ps
8
Notes 2, 3, 4
T5
BCLK Rise Time
175
467
550
ps
8
Notes 2, 6, 8
Notes 2, 6, 9
T6
BCLK Fall Time
175
467
550
ps
8
Notes 2, 6, 8
Notes 2, 6, 9
Vcross for 1V swing
0.51
0.76
V
7
Note 7
Rise/Fall Time Matching
325
ps
7
Note 5
BCLK Duty Cycle
45%
55%
8
Note 2
NOTES:
1.
All AC timings for AGTL and CMOS signals are referenced to the BCLK and BCLK# crossing point.
2.
Measured on differential waveform: defined as (BCLK - BCLK#).
3.
Not 100% tested. Specified by design/characterization.
4.
Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that the clock driver be
designed to meet a period stability specification into a test load of 10 to 20 pF. This should be measured on the
rising edge of adjacent BCLKs at the BCLK, BCLK# crossing point. The jitter present must be accounted for as
a component of BCLK skew between devices. Period difference is measured around 0 V crossing points.
5.
Measurement taken from common mode waveform, measure rise/fall time from 0.41 to 0.86 V. Rise/fall time
matching is defined as “the instantaneous difference between maximum BCLK rise (fall) and minimum BCLK#
fall (rise) time, or minimum BCLK rise (fall) and maximum BCLK# fall (rise) time ”. This parameter is designed to
guard waveform symmetry.
6.
Rise time is measured from -0.35 V to 0.35 V and fall time is measured from 0.35 V to -0.35 V.
7.
Measured on common mode waveform - includes every rise/fall crossing.
8.
Measured at the package ball for the Micro-FCBGA package.
9.
Measured at the socket pin for the Micro-FCPGA package.
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