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参数资料
| 型号： | RJ80530LZ001512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | MICRO, FCPGA-478 |
| 文件页数： | 86/96页 |
| 文件大小： | 2018K |
| 代理商： | RJ80530LZ001512 |
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Processor Interface
R
Mobile Intel
Pentium III Processor-M Datasheet
87
RS[2:0]# (I/O - AGTL)
The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for
completion of the current transaction) and must be connected to the appropriate pins/balls on both
agents on the system bus.
RSP# (I - AGTL)
The RSP# (Response Parity) signal is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#. RSP# provides parity protection
for RS[2:0]#. RSP# should be connected to the appropriate pins/balls on both agents on the system bus.
A correct parity signal is high if an even number of covered signals are low, and it is low if an odd
number of covered signals are low. During Idle state of RS[2:0]# (RS[2:0]#=000), RSP# is also high
since it is not driven by any agent guaranteeing correct parity.
RTTIMPEDP (I-Analog)
The RTTIMPEDP (RTT Impedance/PMOS) signal is used to configure the on-die AGTL termination.
Connect the RTTIMPEDP signal to VSS with a 56.2-, 1% resistor.
SMI# (I - 1.5 V Tolerant)
The SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a
System Management Interrupt, the processor saves the current state and enters System Management
Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program
execution from the SMM handler.
STPCLK# (I - 1.5 V Tolerant)
The STPCLK# (Stop Clock) signal, when asserted, causes the processor to enter a low-power Quick
Start state. The processor issues a Stop Grant Acknowledge special transaction and stops providing
internal clock signals to all units except the bus and APIC units. The processor continues to snoop bus
transactions and service interrupts while in the Quick Start state. When STPCLK# is deasserted and
other conditions in are met, the processor restarts its internal clock to all units and resumes execution.
The assertion of STPCLK# has no affect on the bus clock.
TCK (I - 1.5 V Tolerant)
The TCK (Test Clock) signal provides the clock input for the test bus (also known as the test access
port).
TDI (I - 1.5 V Tolerant)
The TDI (Test Data In) signal transfers serial test data to the processor. TDI provides the serial input
needed for JTAG support.
TDO (O - 1.5 V Tolerant Open-drain)
The TDO (Test Data Out) signal transfers serial test data from the processor. TDO provides the serial
output needed for JTAG support.
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