- 您现在的位置：买卖IC网 > PDF目录69321 > RJ80530LZ001512 (INTEL CORP) 32-BIT, 1000 MHz, MICROPROCESSOR, CPGA478 PDF资料下载
参数资料
| 型号： | RJ80530LZ001512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | MICRO, FCPGA-478 |
| 文件页数： | 85/96页 |
| 文件大小： | 2018K |
| 代理商： | RJ80530LZ001512 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页当前第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页
Processor Interface
R
86
Mobile Intel
Pentium III Processor-M Datasheet
PWRGOOD (I – 1.8 V Tolerant)
PWRGOOD (Power Good) is a 1.8-V tolerant input. The processor requires this signal to be a clean
indication that clocks and the power supplies (VCC, VCCT, etc.) are stable and within their
specifications. Clean implies that the signal will remain low, (capable of sinking leakage current) and
without glitches, from the time that the power supplies are turned on, until they come within
specification. The signal will then transition monotonically to a high (1.8V) state. Figure 12 through
Figure 14 illustrate the relationship of PWRGOOD to other system signals. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before the rising edge of PWRGOOD.
It must also meet the minimum pulse width specified in Table 24 (Section 3.7) and be followed by a
1 ms RESET# pulse. PWRGOOD may be asserted before BCLK is active (please refer to Table 24,
Note 5).
The PWRGOOD signal, which must be supplied to the processor, is used to protect internal circuits
against voltage sequencing issues. The PWRGOOD signal should be driven high throughout boundary
scan operation.
REQ[4:0]# (I/O - AGTL)
The REQ[4:0]# (Request Command) signals must be connected to the appropriate pins/balls on both
agents on the system bus. They are asserted by the current bus owner when it drives A[35:3]# to define
the currently active transaction type.
RESET# (I - AGTL)
Asserting the RESET# signal resets the processor to a known state and invalidates the L1 and L2
caches without writing back Modified (M state) lines. For a power-on type reset, RESET# must stay
active for at least 1 ms after VCC and BCLK, BCLK# have reached their proper DC and AC
specifications and after PWRGOOD has been asserted. When observing active RESET#, all bus agents
will deassert their outputs within two clocks. RESET# is the only AGTL signal that does not have on-
die AGTL termination. A 56.2-
, 1% terminating resistor connected to VCCT is required.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for the power-on
configuration. The configuration options are described in Section 4 and in the P6 Family of Processors
Developer’s Manual.
Unless its outputs are tri-stated during power-on configuration, after an active-to-inactive transition of
RESET#, the processor optionally executes its built-in self-test (BIST) and begins program execution
at reset-vector 000FFFF0H or FFFFFFF0H. RESET# must be connected to the appropriate pins/balls
on both agents on the system bus.
RP# (I/O - AGTL)
The RP# (Request Parity) signal is driven by the request initiator and provides parity protection on
ADS# and REQ[4:0]#. RP# should be connected to the appropriate pins/balls on both agents on the
system bus.
A correct parity signal is high if an even number of covered signals is low and low if an odd number of
covered signals are low. This definition allows parity to be high when all covered signals are high.
相关PDF资料 |
PDF描述 |
|---|---|
| RH80530GZ012512 | 32-BIT, 1266 MHz, MICROPROCESSOR, CPGA478 |
| RH80530NZ006256 | 32-BIT, 1133 MHz, MICROPROCESSOR, CPGA478 |
| RJ80530VZ733256 | 32-BIT, 733 MHz, MICROPROCESSOR, PBGA479 |
| RH80530NZ001256 | 32-BIT, 1000 MHz, MICROPROCESSOR, CPGA478 |
| RJ80530VY700256 | 32-BIT, 700 MHz, MICROPROCESSOR, PBGA479 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| RJ80530LZ733512 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| RJ80530LZ733512S L5QS | 制造商:Intel 功能描述:MPU Pentium? III Processor 64-Bit 0.13um 733MHz 479-Pin uFCBGA |
| RJ80530LZ866512 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| RJ80530LZ933512 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| RJ80530LZ933512S L68W | 制造商:Intel 功能描述:MPU Pentium? III Processor-M 64-Bit 0.13um 933MHz 479-Pin uFCBGA |
发布紧急采购，3分钟左右您将得到回复。